Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

I-Min Liu; Tan-Li Chou; Adnan Aziz; D. F. Wong

doi:10.1145/332357.332370

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

53 Citations (Scopus)

Abstract

We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform clock routing while simultaneously considering wire sizing and buffer insertion. We introduce wire widths and levels of buffers inserted as variables in forming merging segments in the proposed Integrated Deferred-Merge Embedding (IDME) algorithm. As a result, more zero-skew merging locations are made possible and the clock trees generated are zero-skew by construction. Our experiments show that by taking the advantage offered by wire sizing, we are able to minimize phase delay as well as to reduce wire length and use less buffers.

Original language	English
Title of host publication	ISPD '00
Subtitle of host publication	Proceedings of the 2000 International Symposium on Physical Design
Publisher	Association for Computing Machinery (ACM)
Pages	33-38
Number of pages	6
ISBN (Print)	9781581131918
DOIs	https://doi.org/10.1145/332357.332370
Publication status	Published - May 2000
Event	2000 International Symposium on Physical Design, ISPD 2000 - San Diego, United States Duration: 9 Apr 2000 → 12 Apr 2000 https://dl.acm.org/doi/proceedings/10.1145/332357 (Conference proceedings )

Publication series

Name	Proceedings of the International Symposium on Physical Design, ISPD

Symposium

Symposium	2000 International Symposium on Physical Design, ISPD 2000
Country/Territory	United States
City	San Diego
Period	9/04/00 → 12/04/00
Internet address	https://dl.acm.org/doi/proceedings/10.1145/332357 (Conference proceedings )

Scopus Subject Areas

Electrical and Electronic Engineering

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10.1145/332357.332370

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Liu, I.-M., Chou, T.-L., Aziz, A., & Wong, D. F. (2000). Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. In ISPD '00: Proceedings of the 2000 International Symposium on Physical Design (pp. 33-38). (Proceedings of the International Symposium on Physical Design, ISPD). Association for Computing Machinery (ACM). https://doi.org/10.1145/332357.332370

@inproceedings{2a174f85185d40c893345d1caa80f6aa,

title = "Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion",

abstract = "We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform clock routing while simultaneously considering wire sizing and buffer insertion. We introduce wire widths and levels of buffers inserted as variables in forming merging segments in the proposed Integrated Deferred-Merge Embedding (IDME) algorithm. As a result, more zero-skew merging locations are made possible and the clock trees generated are zero-skew by construction. Our experiments show that by taking the advantage offered by wire sizing, we are able to minimize phase delay as well as to reduce wire length and use less buffers.",

author = "I-Min Liu and Tan-Li Chou and Adnan Aziz and Wong, {D. F.}",

year = "2000",

month = may,

doi = "10.1145/332357.332370",

language = "English",

isbn = "9781581131918",

series = "Proceedings of the International Symposium on Physical Design, ISPD",

publisher = "Association for Computing Machinery (ACM)",

pages = "33--38",

booktitle = "ISPD '00",

address = "United States",

note = "2000 International Symposium on Physical Design, ISPD 2000 ; Conference date: 09-04-2000 Through 12-04-2000",

url = "https://dl.acm.org/doi/proceedings/10.1145/332357",

}

Liu, I-M, Chou, T-L, Aziz, A & Wong, DF 2000, Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. in ISPD '00: Proceedings of the 2000 International Symposium on Physical Design. Proceedings of the International Symposium on Physical Design, ISPD, Association for Computing Machinery (ACM), pp. 33-38, 2000 International Symposium on Physical Design, ISPD 2000, San Diego, California, United States, 9/04/00. https://doi.org/10.1145/332357.332370

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. / Liu, I-Min; Chou, Tan-Li; Aziz, Adnan et al.
ISPD '00: Proceedings of the 2000 International Symposium on Physical Design. Association for Computing Machinery (ACM), 2000. p. 33-38 (Proceedings of the International Symposium on Physical Design, ISPD).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

AU - Liu, I-Min

AU - Chou, Tan-Li

AU - Aziz, Adnan

AU - Wong, D. F.

PY - 2000/5

Y1 - 2000/5

N2 - We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform clock routing while simultaneously considering wire sizing and buffer insertion. We introduce wire widths and levels of buffers inserted as variables in forming merging segments in the proposed Integrated Deferred-Merge Embedding (IDME) algorithm. As a result, more zero-skew merging locations are made possible and the clock trees generated are zero-skew by construction. Our experiments show that by taking the advantage offered by wire sizing, we are able to minimize phase delay as well as to reduce wire length and use less buffers.

AB - We propose an integrated clock tree construction algorithm which performs simultaneous routing, wire sizing and buffer insertion. In existing approaches, wire sizing and clock buffer insertion are typically applied sequentially after a clock tree is generated and routed, i.e., they are done as post-processing steps. None of the known methods can perform clock routing while simultaneously considering wire sizing and buffer insertion. We introduce wire widths and levels of buffers inserted as variables in forming merging segments in the proposed Integrated Deferred-Merge Embedding (IDME) algorithm. As a result, more zero-skew merging locations are made possible and the clock trees generated are zero-skew by construction. Our experiments show that by taking the advantage offered by wire sizing, we are able to minimize phase delay as well as to reduce wire length and use less buffers.

UR - http://www.scopus.com/inward/record.url?scp=0033702370&partnerID=8YFLogxK

U2 - 10.1145/332357.332370

DO - 10.1145/332357.332370

M3 - Conference proceeding

AN - SCOPUS:0033702370

SN - 9781581131918

T3 - Proceedings of the International Symposium on Physical Design, ISPD

SP - 33

EP - 38

BT - ISPD '00

PB - Association for Computing Machinery (ACM)

T2 - 2000 International Symposium on Physical Design, ISPD 2000

Y2 - 9 April 2000 through 12 April 2000

ER -

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion

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