Abstract
Wire shaping for delay/power minimization has been extensively studied. Due to the perceived high design and manufacturing costs for using non-uniform wire shapes, wire shaping is generally considered to be impractical. In this paper, we present a practical wire shaping methodology. Non-uniform wire shapes are directly implemented on silicon wafer instead of in GDSII during design. We present novel enhancements to existing OPC technology to accurately print non-uniform wire shapes. Experimental results show that the post-OPC mask complexities of uniform wire and non-uniform wire are comparable. With minimal impact on the design and manufacturing flows and minimal additional design and manufacturing costs, we demonstrate that wire shaping can help to obtain substantial reduction of interconnect dynamic power without affecting timing closure. Our wire shaping methodology is an excellent example of Manufacturing for Design.
Original language | English |
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Title of host publication | ISPD '09 |
Subtitle of host publication | Proceedings of the 2009 International Symposium on Physical Design |
Publisher | Association for Computing Machinery (ACM) |
Pages | 131-138 |
Number of pages | 8 |
ISBN (Print) | 9781605584492 |
DOIs | |
Publication status | Published - 29 Mar 2009 |
Event | 18th International Symposium on Physical Design, ISPD 2009 - San Diego, United States Duration: 29 Mar 2009 → 1 Apr 2009 https://dl.acm.org/doi/proceedings/10.1145/1514932 (Conference proceedings) |
Publication series
Name | Proceedings of the International Symposium on Physical Design, ISPD |
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Symposium
Symposium | 18th International Symposium on Physical Design, ISPD 2009 |
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Country/Territory | United States |
City | San Diego |
Period | 29/03/09 → 1/04/09 |
Internet address |
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User-Defined Keywords
- Wire tapering
- Power Minimization
- Interconnect
- OPC
- Manufacturing for Design