Wire planning with bounded over-the-block wires

Hua Xiang; I Min Liu; Martin D. F. Wong

doi:10.1109/ISQED.2005.130

Wire planning with bounded over-the-block wires

Hua Xiang, I Min Liu, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

1 Citation (Scopus)

Abstract

The hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the low-level designs have to have a global view of high-level object connections so that some resources can be allocated in advance, and this makes wire planning an important issue in physical design. In this paper, we present two exact polynomial-time algorithms for wire planning with bounded over-the-block wires. The constraints on over-the-block wires help the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. Both algorithms guarantee to find an optimal routing solution for a two-pin net as long as one exists. One requires less memory, while the other may take less running time when processing a large number of nets. According to different application requirements, users can choose an appropriate one.

Original language	English
Title of host publication	Proceedings of 6th International Symposium on Quality Electronic Design, ISQED 2005
Place of Publication	United States
Publisher	IEEE
Pages	622-627
Number of pages	6
ISBN (Print)	0769523013, 9780769523019
DOIs	https://doi.org/10.1109/ISQED.2005.130
Publication status	Published - Mar 2005
Event	6th International Symposium on Quality Electronic Design, ISQED 2005 - San Jose, United States Duration: 21 Mar 2005 → 23 Mar 2005 https://www.isqed.org/English/Archives/2005/index.html (Conference website) https://www.isqed.org/English/Archives/2005/Program/Advance-Program-Rev7.pdf (Conference program) https://ieeexplore.ieee.org/xpl/conhome/9684/proceeding (Conference proceedings)

Publication series

Name	Proceedings of International Symposium on Quality Electronic Design, ISQED
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Symposium

Symposium	6th International Symposium on Quality Electronic Design, ISQED 2005
Country/Territory	United States
City	San Jose
Period	21/03/05 → 23/03/05
Internet address	https://www.isqed.org/English/Archives/2005/index.html (Conference website) https://www.isqed.org/English/Archives/2005/Program/Advance-Program-Rev7.pdf (Conference program) https://ieeexplore.ieee.org/xpl/conhome/9684/proceeding (Conference proceedings)

Scopus Subject Areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

User-Defined Keywords

over-the-block
routing
wire planning

Access to Document

10.1109/ISQED.2005.130

Cite this

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title = "Wire planning with bounded over-the-block wires",

abstract = "The hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the low-level designs have to have a global view of high-level object connections so that some resources can be allocated in advance, and this makes wire planning an important issue in physical design. In this paper, we present two exact polynomial-time algorithms for wire planning with bounded over-the-block wires. The constraints on over-the-block wires help the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. Both algorithms guarantee to find an optimal routing solution for a two-pin net as long as one exists. One requires less memory, while the other may take less running time when processing a large number of nets. According to different application requirements, users can choose an appropriate one.",

keywords = "over-the-block, routing, wire planning",

author = "Hua Xiang and Liu, {I Min} and Wong, {Martin D. F.}",

note = "Funding information: This work was partially supported by the National Science Foundation under grant CCR-0306244. Publisher copyright: {\textcopyright} 2005 by The Institute of Electrical and Electronics Engineers, Inc. ; 6th International Symposium on Quality Electronic Design, ISQED 2005 ; Conference date: 21-03-2005 Through 23-03-2005",

year = "2005",

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doi = "10.1109/ISQED.2005.130",

language = "English",

isbn = "0769523013",

series = "Proceedings of International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE",

pages = "622--627",

booktitle = "Proceedings of 6th International Symposium on Quality Electronic Design, ISQED 2005",

address = "United States",

url = "https://www.isqed.org/English/Archives/2005/index.html, https://www.isqed.org/English/Archives/2005/Program/Advance-Program-Rev7.pdf, https://ieeexplore.ieee.org/xpl/conhome/9684/proceeding",

}

Xiang, H, Liu, IM & Wong, MDF 2005, Wire planning with bounded over-the-block wires. in Proceedings of 6th International Symposium on Quality Electronic Design, ISQED 2005., 1410654, Proceedings of International Symposium on Quality Electronic Design, ISQED, IEEE, United States, pp. 622-627, 6th International Symposium on Quality Electronic Design, ISQED 2005, San Jose, California, United States, 21/03/05. https://doi.org/10.1109/ISQED.2005.130

Wire planning with bounded over-the-block wires. / Xiang, Hua; Liu, I Min; Wong, Martin D. F.
Proceedings of 6th International Symposium on Quality Electronic Design, ISQED 2005. United States: IEEE, 2005. p. 622-627 1410654 (Proceedings of International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Xiang, Hua

AU - Liu, I Min

AU - Wong, Martin D. F.

N1 - Funding information: This work was partially supported by the National Science Foundation under grant CCR-0306244. Publisher copyright: © 2005 by The Institute of Electrical and Electronics Engineers, Inc.

PY - 2005/3

Y1 - 2005/3

N2 - The hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the low-level designs have to have a global view of high-level object connections so that some resources can be allocated in advance, and this makes wire planning an important issue in physical design. In this paper, we present two exact polynomial-time algorithms for wire planning with bounded over-the-block wires. The constraints on over-the-block wires help the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. Both algorithms guarantee to find an optimal routing solution for a two-pin net as long as one exists. One requires less memory, while the other may take less running time when processing a large number of nets. According to different application requirements, users can choose an appropriate one.

AB - The hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the low-level designs have to have a global view of high-level object connections so that some resources can be allocated in advance, and this makes wire planning an important issue in physical design. In this paper, we present two exact polynomial-time algorithms for wire planning with bounded over-the-block wires. The constraints on over-the-block wires help the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. Both algorithms guarantee to find an optimal routing solution for a two-pin net as long as one exists. One requires less memory, while the other may take less running time when processing a large number of nets. According to different application requirements, users can choose an appropriate one.

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Wire planning with bounded over-the-block wires

Abstract

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Symposium

Scopus Subject Areas

User-Defined Keywords

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