Abstract
The need for a two-way interaction between logic synthesis and FPGA logic module design has been stressed recently. Having a logic module that can implement many functions is a good idea only if one can also give a synthesis strategy that makes efficient use of this functionality. Traditionally technology mapping algorithms have been developed after the logic architecture has been designed. We follow a dual approach, by focusing on a specific technology mapping algorithm, namely the structural tree-based mapping algorithm, and designing a logic module that can be mapped efficiently by this algorithm. It is known that the tree-based mapping algorithm makes optimal use of a library of functions, each of which can be represented by a tree of AND, OR and NOT gates (seriesparallel or SP functions). We show how to design a SP function with a minimum number of inputs, that can implement all possible SP functions with a specified number of inputs. For instance, we demonstrate a 7-input SP function that can implement all 4-input SP functions. Mapping results show that, on an average, the number blocks of this function needed to map benchmark circuits is 12% less than that for Actel's ACTl logic modules. Our logic modules show a 4% improvement over ACTl, if the block count is scaled to take into account the number of transistors needed to implement different logic modules.
Original language | English |
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Title of host publication | 1996 ACM 4th International Symposium on Field-Programmable Gate Arrays, FPGA 1996 |
Publisher | IEEE |
Pages | 31-37 |
Number of pages | 7 |
ISBN (Print) | 9780897917735 |
DOIs | |
Publication status | Published - Feb 1996 |
Event | 4th ACM International Symposium on Field-Programmable Gate Arrays, FPGA 1996 - Napa Valley, United States Duration: 11 Feb 1996 → 13 Feb 1996 https://ieeexplore.ieee.org/xpl/conhome/9475/proceeding (Conference proceedings) https://dl.acm.org/doi/proceedings/10.1145/228370 (Conference proceedings) |
Publication series
Name | Proceedings of the 1996 ACM 4th International Symposium on Field-Programmable Gate Arrays, FPGA 1996 |
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Conference
Conference | 4th ACM International Symposium on Field-Programmable Gate Arrays, FPGA 1996 |
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Country/Territory | United States |
City | Napa Valley |
Period | 11/02/96 → 13/02/96 |
Internet address |
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Scopus Subject Areas
- Hardware and Architecture
- Electrical and Electronic Engineering