Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology

Qiang Ma; Hongbo Zhang; Martin D.F. Wong

doi:10.1145/2228360.2228468

Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology

Qiang Ma^*, Hongbo Zhang, Martin D.F. Wong

^*Corresponding author for this work

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

51 Citations (Scopus)

Abstract

As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural extension along the paradigm of DPL. With an extra mask to accommodate the features, TPL can be used to eliminate the unresolvable conflicts and minimize the number of stitches, which are pervasive in DPL process, and thus smoothen the layout decomposition step. Considering TPL during routing stage explores a larger solution space and can further improve the layout decomposability. In this paper, we propose the first triple patterning aware detailed routing scheme, and compare its performance with the double patterning version in 14nm node. Experimental results show that, using TPL, the conflicts can be resolved much more easily and the stitches can be significantly reduced in contrast to DPL.

Original language	English
Title of host publication	49th ACM/IEEE Design Automation Conference - Proceedings 2012
Editors	Patrick Groeneveld
Publisher	Association for Computing Machinery (ACM)
Pages	591-596
Number of pages	6
ISBN (Print)	9781450311991
DOIs	https://doi.org/10.1145/2228360.2228468
Publication status	Published - 3 Jun 2012
Event	49th ACM/IEEE Design Automation Conference, DAC 2012 - San Francisco, United States Duration: 3 Jun 2012 → 7 Jun 2012 https://dl.acm.org/doi/proceedings/10.1145/2228360 https://ieeexplore.ieee.org/xpl/conhome/6235084/proceeding

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Conference

Conference	49th ACM/IEEE Design Automation Conference, DAC 2012
Country/Territory	United States
City	San Francisco
Period	3/06/12 → 7/06/12
Internet address	https://dl.acm.org/doi/proceedings/10.1145/2228360 https://ieeexplore.ieee.org/xpl/conhome/6235084/proceeding

Scopus Subject Areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

User-Defined Keywords

14nm technology
double patterning aware routing
maze routing
triple patterning aware routing

Access to Document

10.1145/2228360.2228468

Cite this

Ma, Q., Zhang, H., & Wong, M. D. F. (2012). Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. In P. Groeneveld (Ed.), 49th ACM/IEEE Design Automation Conference - Proceedings 2012 (pp. 591-596). (ACM/IEEE Design Automation Conference - Proceedings). Association for Computing Machinery (ACM). https://doi.org/10.1145/2228360.2228468

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title = "Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology",

abstract = "As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural extension along the paradigm of DPL. With an extra mask to accommodate the features, TPL can be used to eliminate the unresolvable conflicts and minimize the number of stitches, which are pervasive in DPL process, and thus smoothen the layout decomposition step. Considering TPL during routing stage explores a larger solution space and can further improve the layout decomposability. In this paper, we propose the first triple patterning aware detailed routing scheme, and compare its performance with the double patterning version in 14nm node. Experimental results show that, using TPL, the conflicts can be resolved much more easily and the stitches can be significantly reduced in contrast to DPL.",

keywords = "14nm technology, double patterning aware routing, maze routing, triple patterning aware routing",

author = "Qiang Ma and Hongbo Zhang and Wong, {Martin D.F.}",

note = "Funding Information: This work was partially supported by the National Science Foundation under grant CCF-1017516 and a grant from the semiconductor Research Corporation (SRC). Publisher copyright: {\textcopyright} 2012 ACM; 49th ACM/IEEE Design Automation Conference, DAC 2012 ; Conference date: 03-06-2012 Through 07-06-2012",

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doi = "10.1145/2228360.2228468",

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Ma, Q, Zhang, H & Wong, MDF 2012, Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. in P Groeneveld (ed.), 49th ACM/IEEE Design Automation Conference - Proceedings 2012. ACM/IEEE Design Automation Conference - Proceedings, Association for Computing Machinery (ACM), pp. 591-596, 49th ACM/IEEE Design Automation Conference, DAC 2012, San Francisco, California, United States, 3/06/12. https://doi.org/10.1145/2228360.2228468

Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. / Ma, Qiang; Zhang, Hongbo; Wong, Martin D.F.
49th ACM/IEEE Design Automation Conference - Proceedings 2012. ed. / Patrick Groeneveld. Association for Computing Machinery (ACM), 2012. p. 591-596 (ACM/IEEE Design Automation Conference - Proceedings).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Ma, Qiang

AU - Zhang, Hongbo

AU - Wong, Martin D.F.

N1 - Funding Information: This work was partially supported by the National Science Foundation under grant CCF-1017516 and a grant from the semiconductor Research Corporation (SRC). Publisher copyright: © 2012 ACM

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Y1 - 2012/6/3

N2 - As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural extension along the paradigm of DPL. With an extra mask to accommodate the features, TPL can be used to eliminate the unresolvable conflicts and minimize the number of stitches, which are pervasive in DPL process, and thus smoothen the layout decomposition step. Considering TPL during routing stage explores a larger solution space and can further improve the layout decomposability. In this paper, we propose the first triple patterning aware detailed routing scheme, and compare its performance with the double patterning version in 14nm node. Experimental results show that, using TPL, the conflicts can be resolved much more easily and the stitches can be significantly reduced in contrast to DPL.

AB - As technology continues to scale to 14nm node, Double Patterning Lithography (DPL) is pushed to near its limit. Triple Patterning Lithography (TPL) is a considerable and natural extension along the paradigm of DPL. With an extra mask to accommodate the features, TPL can be used to eliminate the unresolvable conflicts and minimize the number of stitches, which are pervasive in DPL process, and thus smoothen the layout decomposition step. Considering TPL during routing stage explores a larger solution space and can further improve the layout decomposability. In this paper, we propose the first triple patterning aware detailed routing scheme, and compare its performance with the double patterning version in 14nm node. Experimental results show that, using TPL, the conflicts can be resolved much more easily and the stitches can be significantly reduced in contrast to DPL.

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ER -

Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology

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