Timing-driven routing for symmetrical-array-based FPGAs

Kai Zhu, Yao-Wen Chang, D. F. Wong

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

11 Citations (Scopus)


In this paper, we present a timing-driven global router for symmetrical-array-based FPGAs. The routing resources in the symmetrical-array-based FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, traditional measure of routing delay based on the geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing trees, arising from the special properties of FPGA routing architectures. We explore the complexity of the routing-tree problem and present efficient and effective approximation algorithms for the problem. Based on the solutions to the routing-tree problem, we present a global-routing algorithm which is able to utilize various routing segments with global consideration to meet the timing constraints. Experimental results on benchmark circuits show that our approach is promising.
Original languageEnglish
Title of host publicationProceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998
Number of pages6
ISBN (Print)0818690992
Publication statusPublished - 5 Oct 1998
Event16th IEEE International Conference on Computer Design, ICCD 1998 - Austin, United States
Duration: 5 Oct 19987 Oct 1998
https://ieeexplore.ieee.org/xpl/conhome/5873/proceeding (Conference proceedings)

Publication series

NameProceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors
ISSN (Print)1063-6404
ISSN (Electronic)2576-6996


Conference16th IEEE International Conference on Computer Design, ICCD 1998
Country/TerritoryUnited States
Internet address


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