Temperature-aware placement for SOCs

Jeng-Llang Tsai*, C.C.-P. Chen, Guoqiang Chen, B. Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, M. D. F. Wong, S. S. Sapatnekar

*Corresponding author for this work

Research output: Contribution to journalJournal articlepeer-review

47 Citations (Scopus)


Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high-quality, accurate thermal modeling and analysis, and thermally oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods, such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, two-dimensional and three-dimensional thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.

Original languageEnglish
Pages (from-to)1502-1517
Number of pages16
JournalProceedings of the IEEE
Issue number8
Publication statusPublished - Aug 2006

Scopus Subject Areas

  • Computer Science(all)
  • Electrical and Electronic Engineering

User-Defined Keywords

  • Physical design
  • Placement
  • Thermal analysis
  • Thermal simulation


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