Switch bound allocation for maximizing routability in timing-driven routing of FPGAs

Kai Zhu, D. F. Wong

Research output: Chapter in book/report/conference proceedingChapterpeer-review


In segmented channel routing of row-based FPGAs, the routability and interconnection delays depend on the choice of the upper bounds on the number of programmable switches used in routing net segments in the channel. Traditionally, the upper bounds for the net segments in the same channel are set uniformly. In this paper, we present algorithms for determining the upper bounds for all net segments of a net simultaneously, so that the predefined source-to-sink delay bound on the net is satisfied and the routability of the net is maximized. The upper bounds on net segments in a channel thus in general are non-uniform. Preliminary experimental results show that the algorithms can significantly improve routability and reduce delay bound violation as compared with the traditional approach.

Original languageEnglish
Title of host publication31st ACM/IEEE Design Automation Conference - Proceedings 1994
PublisherAssociation for Computing Machinery (ACM)
Number of pages6
ISBN (Print)9780897916530, 0897916530
Publication statusPublished - Jun 1994
Event31st ACM/IEEE-CAS/EDAC Design Automation Conference, DAC 1994 - San Diego, United States
Duration: 6 Jun 199410 Jun 1994
https://dl.acm.org/doi/proceedings/10.1145/196244 (Link to conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference31st ACM/IEEE-CAS/EDAC Design Automation Conference, DAC 1994
Country/TerritoryUnited States
CitySan Diego
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Control and Systems Engineering


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