TY - JOUR
T1 - Slicing floorplans with boundary constraints
AU - Young, F. Y.
AU - Wong, D. F.
AU - Yang, H. H.
N1 - Funding Information:
Manuscript received November 17, 1998; revised February 5, 1999. This work was supported in part by the Texas Advanced Research Program and in part by a grant from the Intel Corporation. This paper was recommended by Associate Editor C.-K. Cheng. F. Y. Young and D. F. Wong are with the Department of Computer Sciences, The University of Texas at Austin, Austin, TX 78712-1188 USA. H. H. Yang is with the Intel Corporation, Hillsboro, OR 97124-5961 USA. Publisher Item Identifier S 0278-0070(99)06618-X.
PY - 1999/9
Y1 - 1999/9
N2 - In floorplanning of very large scale integration design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom, or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplan algorithm to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solutions in the simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.
AB - In floorplanning of very large scale integration design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom, or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplan algorithm to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solutions in the simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.
UR - http://www.scopus.com/inward/record.url?scp=0032595824&partnerID=8YFLogxK
U2 - 10.1109/43.784129
DO - 10.1109/43.784129
M3 - Journal article
AN - SCOPUS:0032595824
SN - 0278-0070
VL - 18
SP - 1385
EP - 1389
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 9
ER -