Slicing floorplans with boundary constraint

F. Y. Young; D. F. Wong

doi:10.1109/ASPDAC.1999.759699

Slicing floorplans with boundary constraint

F. Y. Young, D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

Abstract

In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solution in a simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.

Original language	English
Title of host publication	Proceedings of The 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Publisher	IEEE
Pages	17-20
Number of pages	4
ISBN (Print)	078035012X
DOIs	https://doi.org/10.1109/ASPDAC.1999.759699
Publication status	Published - 18 Jan 1999
Event	4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Hong Kong, Hong Kong Duration: 18 Jan 1999 → 21 Jan 1999 https://www.aspdac.com/aspdac2011/history/ (Conference website ) https://ieeexplore.ieee.org/xpl/conhome/6092/proceeding (Conference proceedings)

Publication series

Name	Proceedings of The Asia and South Pacific Conference on Design Automation, ASP-DAC

Conference

Conference	4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Country/Territory	Hong Kong
City	Hong Kong
Period	18/01/99 → 21/01/99
Internet address	https://www.aspdac.com/aspdac2011/history/ (Conference website ) https://ieeexplore.ieee.org/xpl/conhome/6092/proceeding (Conference proceedings)

Access to Document

10.1109/ASPDAC.1999.759699

Cite this

@inproceedings{7448ae8ec1d74db8b892a8ae43fca6e0,

title = "Slicing floorplans with boundary constraint",

abstract = "In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solution in a simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.",

author = "Young, {F. Y.} and Wong, {D. F.}",

year = "1999",

month = jan,

day = "18",

doi = "10.1109/ASPDAC.1999.759699",

language = "English",

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series = "Proceedings of The Asia and South Pacific Conference on Design Automation, ASP-DAC",

publisher = "IEEE",

pages = "17--20",

booktitle = "Proceedings of The 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999",

address = "United States",

note = "4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 ; Conference date: 18-01-1999 Through 21-01-1999",

url = "https://www.aspdac.com/aspdac2011/history/, https://ieeexplore.ieee.org/xpl/conhome/6092/proceeding",

}

Young, FY & Wong, DF 1999, Slicing floorplans with boundary constraint. in Proceedings of The 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999. Proceedings of The Asia and South Pacific Conference on Design Automation, ASP-DAC, IEEE, pp. 17-20, 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999, Hong Kong, Hong Kong, 18/01/99. https://doi.org/10.1109/ASPDAC.1999.759699

Slicing floorplans with boundary constraint. / Young, F. Y.; Wong, D. F.
Proceedings of The 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999. IEEE, 1999. p. 17-20 (Proceedings of The Asia and South Pacific Conference on Design Automation, ASP-DAC).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - Slicing floorplans with boundary constraint

AU - Young, F. Y.

AU - Wong, D. F.

PY - 1999/1/18

Y1 - 1999/1/18

N2 - In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solution in a simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.

AB - In floorplanning of VLSI design, it is useful if users are allowed to specify some placement constraints in the packing. One particular kind of placement constraints is to pack some modules on one of the four sides: on the left, on the right, at the bottom or at the top of the final floorplan. These are called boundary constraints. In this paper, we enhanced a well-known slicing floorplanner to handle these boundary constraints. Our main contribution is a necessary and sufficient characterization of the Polish expression, a representation of the intermediate solution in a simulated annealing process, so that we can check these constraints efficiently and can fix the expression in case the constraints are violated. We tested our algorithm on some benchmark data and the performance is good.

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M3 - Conference proceeding

SN - 078035012X

T3 - Proceedings of The Asia and South Pacific Conference on Design Automation, ASP-DAC

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BT - Proceedings of The 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999

PB - IEEE

T2 - 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999

Y2 - 18 January 1999 through 21 January 1999

ER -

Slicing floorplans with boundary constraint

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Cite this