Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

47 Citations (Scopus)


During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

Original languageEnglish
Title of host publication36th ACM/IEEE Design Automation Conference - Proceedings 1999
PublisherAssociation for Computing Machinery (ACM)
Number of pages4
ISBN (Print)9781581131093, 1581130929
Publication statusPublished - 21 Jun 1999
Event36th ACM/IEEE Design Automation Conference, DAC 1999 - New Orleans, United States
Duration: 21 Jun 199925 Jun 1999 (Conference proceedings) (Conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Competition36th ACM/IEEE Design Automation Conference, DAC 1999
Country/TerritoryUnited States
CityNew Orleans
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Control and Systems Engineering


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