Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou; D. F. Wong; I-Min Liu; Adnan Aziz

doi:10.1145/309847.309885

Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

47 Citations (Scopus)

Abstract

During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

Original language	English
Title of host publication	36th ACM/IEEE Design Automation Conference - Proceedings 1999
Publisher	Association for Computing Machinery (ACM)
Pages	96-99
Number of pages	4
ISBN (Print)	9781581131093, 1581130929
DOIs	https://doi.org/10.1145/309847.309885 https://doi.org/10.1109/DAC.1999.781279
Publication status	Published - 21 Jun 1999
Event	36th ACM/IEEE Design Automation Conference, DAC 1999 - New Orleans, United States Duration: 21 Jun 1999 → 25 Jun 1999 https://dl.acm.org/doi/proceedings/10.1145/309847 (Conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/6338/proceeding (Conference proceedings)

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Competition

Competition	36th ACM/IEEE Design Automation Conference, DAC 1999
Country/Territory	United States
City	New Orleans
Period	21/06/99 → 25/06/99
Internet address	https://dl.acm.org/doi/proceedings/10.1145/309847 (Conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/6338/proceeding (Conference proceedings)

Scopus Subject Areas

Hardware and Architecture
Control and Systems Engineering

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Zhou, H., Wong, D. F., Liu, I.-M., & Aziz, A. (1999). Simultaneous routing and buffer insertion with restrictions on buffer locations. In 36th ACM/IEEE Design Automation Conference - Proceedings 1999 (pp. 96-99). (ACM/IEEE Design Automation Conference - Proceedings). Association for Computing Machinery (ACM). https://doi.org/10.1145/309847.309885, https://doi.org/10.1109/DAC.1999.781279

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title = "Simultaneous routing and buffer insertion with restrictions on buffer locations",

abstract = "During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.",

author = "Hai Zhou and Wong, {D. F.} and I-Min Liu and Adnan Aziz",

note = "This work was partially supported by a grant from the Intel Corporation.; 36th ACM/IEEE Design Automation Conference, DAC 1999 ; Conference date: 21-06-1999 Through 25-06-1999",

year = "1999",

month = jun,

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doi = "10.1145/309847.309885",

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series = "ACM/IEEE Design Automation Conference - Proceedings",

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booktitle = "36th ACM/IEEE Design Automation Conference - Proceedings 1999",

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Zhou, H, Wong, DF, Liu, I-M & Aziz, A 1999, Simultaneous routing and buffer insertion with restrictions on buffer locations. in 36th ACM/IEEE Design Automation Conference - Proceedings 1999. ACM/IEEE Design Automation Conference - Proceedings, Association for Computing Machinery (ACM), pp. 96-99, 36th ACM/IEEE Design Automation Conference, DAC 1999, New Orleans, Louisiana, United States, 21/06/99. https://doi.org/10.1145/309847.309885, https://doi.org/10.1109/DAC.1999.781279

Simultaneous routing and buffer insertion with restrictions on buffer locations. / Zhou, Hai; Wong, D. F.; Liu, I-Min et al.
36th ACM/IEEE Design Automation Conference - Proceedings 1999. Association for Computing Machinery (ACM), 1999. p. 96-99 (ACM/IEEE Design Automation Conference - Proceedings).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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N1 - This work was partially supported by a grant from the Intel Corporation.

PY - 1999/6/21

Y1 - 1999/6/21

N2 - During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

AB - During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

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ER -

Simultaneous routing and buffer insertion with restrictions on buffer locations

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