Simultaneous routing and buffer insertion with restrictions on buffer locations

Hai Zhou, D. F. Wong, I-Min Liu, A. Aziz

Research output: Contribution to journalJournal articlepeer-review

44 Citations (Scopus)


During the routing of global interconnects, macro blocks form useful routing regions which allow wires to go through but forbid buffers to be inserted. They give restrictions on buffer locations. In this paper, we take these buffer location restrictions into consideration and solve the simultaneous maze routing and buffer insertion problem. Given a block placement defining buffer location restrictions and a pair of pins (a source and a sink), we give a polynomial time exact algorithm to find a buffered route from the source to the sink with minimum Elmore delay.

Original languageEnglish
Pages (from-to)819-824
Number of pages6
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number7
Publication statusPublished - Jul 2000

Scopus Subject Areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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