TY - JOUR
T1 - Simultaneous escape-routing algorithms for via minimization of high-speed boards
AU - Ozdal, Muhammet Mustafa
AU - Wong, Martin D. F.
AU - Honsinger, Philip S.
N1 - Funding Information:
Manuscript received December 4, 2006; revised April 12, 2007. This work was supported in part by the National Science Foundation under Grant CCR-0306244 and in part by an IBM Faculty Award. The preliminary version of this paper was presented in IEEE/ACM ICCAD in November 2005. This paper was recommended by Associate Editor L. Scheffer.
PY - 2008/1
Y1 - 2008/1
N2 - Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board-routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design-cycle times considerably. In this paper, we propose an escape-routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed-design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm show that our algorithm reduces the via requirements of industrial test cases on average by 39%.
AB - Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board-routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design-cycle times considerably. In this paper, we propose an escape-routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed-design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm show that our algorithm reduces the via requirements of industrial test cases on average by 39%.
KW - Design constraints
KW - Escape routing
KW - Package routing
KW - Printed circuit board
KW - Randomized algorithms
KW - Via minimization
UR - http://www.scopus.com/inward/record.url?scp=37249087427&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2007.907274
DO - 10.1109/TCAD.2007.907274
M3 - Journal article
AN - SCOPUS:37249087427
SN - 0278-0070
VL - 27
SP - 84
EP - 94
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 1
ER -