Signal integrity optimization on the pad assignment for high-speed VLSI design

Kai-Yuan Chao; D. F. Wong

doi:10.1109/ICCAD.1995.480253

Signal integrity optimization on the pad assignment for high-speed VLSI design

Kai-Yuan Chao, D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

7 Citations (Scopus)

Abstract

Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simultaneous switching noise and crosstalk that are inevitably caused by package inductance and capacitance during the design of high-speed/high-bandwidth circuits. Due to its efficiency, our algorithm can be incorporated into existing circuit floorplanning and placement schemes for the co-design of VLSI and packaging. For a set of industrial circuits/packages tested in our experiment, on the average, our method achieves a 16.8% reduction of total electrical noise when compared with the conventional design rule of thumb popularly used by circuit designers.

Original language	English
Title of host publication	1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995
Publisher	IEEE
Pages	720-725
Number of pages	6
ISBN (Print)	0818672137, 0818682000
DOIs	https://doi.org/10.1109/ICCAD.1995.480253
Publication status	Published - Nov 1995
Event	1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995 - San Jose, United States Duration: 5 Nov 1995 → 9 Nov 1995 https://ieeexplore.ieee.org/xpl/conhome/3472/proceeding (Link to conference proceedings)

Publication series

Name	Proceedings of 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995

Conference

Conference	1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995
Country/Territory	United States
City	San Jose
Period	5/11/95 → 9/11/95
Internet address	https://ieeexplore.ieee.org/xpl/conhome/3472/proceeding (Link to conference proceedings)

Scopus Subject Areas

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ICCAD.1995.480253

Cite this

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title = "Signal integrity optimization on the pad assignment for high-speed VLSI design",

abstract = "Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simultaneous switching noise and crosstalk that are inevitably caused by package inductance and capacitance during the design of high-speed/high-bandwidth circuits. Due to its efficiency, our algorithm can be incorporated into existing circuit floorplanning and placement schemes for the co-design of VLSI and packaging. For a set of industrial circuits/packages tested in our experiment, on the average, our method achieves a 16.8% reduction of total electrical noise when compared with the conventional design rule of thumb popularly used by circuit designers.",

author = "Kai-Yuan Chao and Wong, {D. F.}",

note = "Funding Information: This work was partially supported by Texas Advanced Research Program under Grant No. 003658459. Publisher Copyright: {\textcopyright} 1995 IEEE ; 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995 ; Conference date: 05-11-1995 Through 09-11-1995",

year = "1995",

month = nov,

doi = "10.1109/ICCAD.1995.480253",

language = "English",

isbn = "0818672137",

series = "Proceedings of 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995",

publisher = "IEEE",

pages = "720--725",

booktitle = "1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/3472/proceeding",

}

Chao, K-Y & Wong, DF 1995, Signal integrity optimization on the pad assignment for high-speed VLSI design. in 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995. Proceedings of 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995, IEEE, pp. 720-725, 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, United States, 5/11/95. https://doi.org/10.1109/ICCAD.1995.480253

Signal integrity optimization on the pad assignment for high-speed VLSI design. / Chao, Kai-Yuan; Wong, D. F.
1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995. IEEE, 1995. p. 720-725 (Proceedings of 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995).

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

TY - CHAP

T1 - Signal integrity optimization on the pad assignment for high-speed VLSI design

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AU - Wong, D. F.

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Y1 - 1995/11

N2 - Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simultaneous switching noise and crosstalk that are inevitably caused by package inductance and capacitance during the design of high-speed/high-bandwidth circuits. Due to its efficiency, our algorithm can be incorporated into existing circuit floorplanning and placement schemes for the co-design of VLSI and packaging. For a set of industrial circuits/packages tested in our experiment, on the average, our method achieves a 16.8% reduction of total electrical noise when compared with the conventional design rule of thumb popularly used by circuit designers.

AB - Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simultaneous switching noise and crosstalk that are inevitably caused by package inductance and capacitance during the design of high-speed/high-bandwidth circuits. Due to its efficiency, our algorithm can be incorporated into existing circuit floorplanning and placement schemes for the co-design of VLSI and packaging. For a set of industrial circuits/packages tested in our experiment, on the average, our method achieves a 16.8% reduction of total electrical noise when compared with the conventional design rule of thumb popularly used by circuit designers.

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M3 - Chapter

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T3 - Proceedings of 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995

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BT - 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995

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T2 - 1995 IEEE International Conference on Computer-Aided Design, ICCAD 1995

Y2 - 5 November 1995 through 9 November 1995

ER -

Signal integrity optimization on the pad assignment for high-speed VLSI design

Abstract

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