TY - JOUR
T1 - Sign-Off Timing Considerations via Concurrent Routing Topology Optimization
AU - Liu, Siting
AU - Wang, Ziyi
AU - Liu, Fangzhou
AU - Lin, Yibo
AU - Yu, Bei
AU - Wong, Martin
N1 - Funding Information:
This work is supported in part by The Research Grants Council of Hong Kong SAR (Project No. CUHK14211824) and the MIND project (MINDXZ202404).
Publisher Copyright:
© 2024 IEEE.
PY - 2024/11/27
Y1 - 2024/11/27
N2 - Timing closure is considered across the circuit design flow. Generally, the early-stage timing optimization can only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path length, since obtaining sign-off performance needs a time-consuming routing flow. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. Therefore, we utilize the power of deep learning techniques to bridge the gap between the early-stage analysis and the sign-off analysis. A well-designed deep learning framework guides the adjustment of Steiner points to enable explicit early-stage timing optimization. Cooperating with deep Steiner point adjustment, we propose the routing topology reconstruction to accelerate the convergence and hold a reasonable routing topology. Further, we also introduce Steiner point simplification as a post-processing technique to avoid unnecessary routing constraints. This paper demonstrates the ability of the learning-Assist framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs. With Steiner point adjustment alone, TSteinerPt, can help the SOTA open-source router to obtain 11.2% and 7.1% improvement for the sign-off worst negative slack and total negative slack, respectively. Under the additional joint optimization with routing topology reconstruction and simplification, TSteinerRec can further save 25.9% optimization duration with a better sign-off performance.
AB - Timing closure is considered across the circuit design flow. Generally, the early-stage timing optimization can only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or pre-routing path length, since obtaining sign-off performance needs a time-consuming routing flow. However, there is no consistency guarantee between early-stage metrics and sign-off timing performance. Therefore, we utilize the power of deep learning techniques to bridge the gap between the early-stage analysis and the sign-off analysis. A well-designed deep learning framework guides the adjustment of Steiner points to enable explicit early-stage timing optimization. Cooperating with deep Steiner point adjustment, we propose the routing topology reconstruction to accelerate the convergence and hold a reasonable routing topology. Further, we also introduce Steiner point simplification as a post-processing technique to avoid unnecessary routing constraints. This paper demonstrates the ability of the learning-Assist framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs. With Steiner point adjustment alone, TSteinerPt, can help the SOTA open-source router to obtain 11.2% and 7.1% improvement for the sign-off worst negative slack and total negative slack, respectively. Under the additional joint optimization with routing topology reconstruction and simplification, TSteinerRec can further save 25.9% optimization duration with a better sign-off performance.
UR - http://www.scopus.com/inward/record.url?scp=85210967858&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2024.3506216
DO - 10.1109/TCAD.2024.3506216
M3 - Journal article
AN - SCOPUS:85210967858
SN - 0278-0070
SP - 1
EP - 13
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ER -