TY - JOUR

T1 - Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance

AU - Gao, Youxin

AU - Wong, D. F.

N1 - Funding Information:
This work was partially supported by the Texas Advanced Research Program under Grant No. 003658288 and by a grant from the Intel Corporation.

PY - 1999/7

Y1 - 1999/7

N2 - In this paper, by using calculus of variations, we determine the optimal shape for a wire under the Elmore delay model. Coupling capacitance has been taken into consideration explicitly by treating it as another source of grounded capacitance. Given two wires in parallel, one has uniform width and the other has non-uniform width whose shape is described by a function f(x). Let TD be the delay through the non-uniform wire. We determine f(x) such that TD is minimized. We also extend our study to the case where a non-uniform wire has two neighboring wires. Our study shows that the optimal shape function satisfies an integral equation. Numerical methods are employed to solve the corresponding differential equation and carry out the integration. We provide an efficient algorithm to find the optimal solution. Experiments show that it only takes several iterations to get the optimal results by using our algorithm. Our experiments also show that the wire delay TD is a convex function of the wire width at the driver end.

AB - In this paper, by using calculus of variations, we determine the optimal shape for a wire under the Elmore delay model. Coupling capacitance has been taken into consideration explicitly by treating it as another source of grounded capacitance. Given two wires in parallel, one has uniform width and the other has non-uniform width whose shape is described by a function f(x). Let TD be the delay through the non-uniform wire. We determine f(x) such that TD is minimized. We also extend our study to the case where a non-uniform wire has two neighboring wires. Our study shows that the optimal shape function satisfies an integral equation. Numerical methods are employed to solve the corresponding differential equation and carry out the integration. We provide an efficient algorithm to find the optimal solution. Experiments show that it only takes several iterations to get the optimal results by using our algorithm. Our experiments also show that the wire delay TD is a convex function of the wire width at the driver end.

UR - http://www.scopus.com/inward/record.url?scp=0032658516&partnerID=8YFLogxK

U2 - 10.1016/S0167-9260(99)00005-X

DO - 10.1016/S0167-9260(99)00005-X

M3 - Journal article

AN - SCOPUS:0032658516

SN - 0167-9260

VL - 27

SP - 165

EP - 178

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

IS - 2

ER -