Abstract
The cost of life testing of integrated circuits (IC's) varies statistically. It is desirable to reduce the testing cost variance in order to reduce the chance of paying a testing cost that is much larger than the mean. In this paper, we study two methods for reducing the testing cost variance. The first method uses the technique of weighted sum of objective functions [1], [2] to integrate the objective of minimizing the mean testing cost and the objective of minimizing the testing cost variance. In the second method, the test engineer inspects the progress of life testing iteratively, collects failure information and then estimates the expected remaining testing cost. If this cost is unacceptably large, he replaces the failed IC's by the functioning ones and/or adds extra IC testers.
| Original language | English |
|---|---|
| Pages (from-to) | 149-152 |
| Number of pages | 4 |
| Journal | IEEE Transactions on Semiconductor Manufacturing |
| Volume | 9 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 29 Feb 1996 |
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This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 9 Industry, Innovation, and Infrastructure
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