TY - JOUR
T1 - Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement
AU - Wu, Huaizhi
AU - Wong, Martin D. F.
AU - Liu, I-Min
AU - Wang, Yusu
N1 - Funding Information:
Manuscript received December 30, 2005; revised May 30, 2006. This work was supported in part by the National Science Foundation under Grant CCR-0306244. This paper was recommended by Associate Editor C. J. Alpert. H. Wu was with Cadence Design Systems, Inc., San Jose, CA 95134 USA. She is now with Atoptech, Inc., Santa Clara, CA 95054 USA (e-mail: [email protected]). M. D. F. Wong is with the Department of Electrical and Computer Engineering, University of Illinois, Urbana–Champaign, IL 61801 USA (e-mail: [email protected]). I-M. Liu is with Atoptech, Inc., Santa Clara, CA 95054 USA (e-mail: [email protected]). Y. Wang is with the Department of Computer Science and Engineering, Ohio State University, Columbus, OH 43210 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCAD.2006.888270
Funding Information:
Dr. Wang is the recipient of the DOE Early Career Principal Investigator Award in 2006. She is a member of the Association for Computing Machinery Computer Society.
PY - 2007/7
Y1 - 2007/7
N2 - High power consumption not only leads to short battery life for hand-held devices but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer grain power and performance tradeoff. In this paper, we propose a methodology on top of a set of algorithms to exploit nontrivial voltage island boundaries for optimal power versus design-cost tradeoff under performance requirement. Our algorithms are efficient, robust, and error-bounded and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a tenfold improvement of our method over current logical-boundary-based industry approach.
AB - High power consumption not only leads to short battery life for hand-held devices but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer grain power and performance tradeoff. In this paper, we propose a methodology on top of a set of algorithms to exploit nontrivial voltage island boundaries for optimal power versus design-cost tradeoff under performance requirement. Our algorithms are efficient, robust, and error-bounded and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a tenfold improvement of our method over current logical-boundary-based industry approach.
KW - low power
KW - optimization
KW - timing
KW - voltage island
UR - http://www.scopus.com/inward/record.url?scp=34250752815&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2006.888270
DO - 10.1109/TCAD.2006.888270
M3 - Journal article
AN - SCOPUS:34250752815
SN - 0278-0070
VL - 26
SP - 1256
EP - 1269
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 7
M1 - 4237245
ER -