Performance-driven board-level routing for FPGA-based logic emulation

W.-K. Mak; D. F. Wong

doi:10.1109/ICCD.1998.727046

Performance-driven board-level routing for FPGA-based logic emulation

W.-K. Mak, D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

Abstract

Previously, two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.

Original language	English
Title of host publication	Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998
Publisher	IEEE
Pages	199-201
Number of pages	3
ISBN (Print)	0818690992
DOIs	https://doi.org/10.1109/ICCD.1998.727046
Publication status	Published - 5 Oct 1998
Event	16th IEEE International Conference on Computer Design, ICCD 1998 - Austin, United States Duration: 5 Oct 1998 → 7 Oct 1998 https://ieeexplore.ieee.org/xpl/conhome/5873/proceeding (Conference proceedings)

Publication series

Name	Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors
ISSN (Print)	1063-6404
ISSN (Electronic)	2576-6996

Conference

Conference	16th IEEE International Conference on Computer Design, ICCD 1998
Country/Territory	United States
City	Austin
Period	5/10/98 → 7/10/98
Internet address	https://ieeexplore.ieee.org/xpl/conhome/5873/proceeding (Conference proceedings)

Access to Document

10.1109/ICCD.1998.727046

Cite this

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title = "Performance-driven board-level routing for FPGA-based logic emulation",

abstract = "Previously, two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.",

author = "W.-K. Mak and Wong, {D. F.}",

year = "1998",

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doi = "10.1109/ICCD.1998.727046",

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series = "Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors",

publisher = "IEEE",

pages = "199--201",

booktitle = "Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998",

address = "United States",

note = "16th IEEE International Conference on Computer Design, ICCD 1998 ; Conference date: 05-10-1998 Through 07-10-1998",

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}

Mak, W-K & Wong, DF 1998, Performance-driven board-level routing for FPGA-based logic emulation. in Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998. Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors, IEEE, pp. 199-201, 16th IEEE International Conference on Computer Design, ICCD 1998, Austin, Texas, United States, 5/10/98. https://doi.org/10.1109/ICCD.1998.727046

Performance-driven board-level routing for FPGA-based logic emulation. / Mak, W.-K.; Wong, D. F.
Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998. IEEE, 1998. p. 199-201 (Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

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N2 - Previously, two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.

AB - Previously, two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.

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U2 - 10.1109/ICCD.1998.727046

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ER -

Performance-driven board-level routing for FPGA-based logic emulation

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