Abstract
In [9] and [10], two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.
Original language | English |
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Title of host publication | FPGA '98 |
Subtitle of host publication | Proceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays |
Publisher | Association for Computing Machinery (ACM) |
Pages | 199-201 |
Number of pages | 3 |
ISBN (Print) | 9780897919784 |
DOIs | |
Publication status | Published - 22 Feb 1998 |
Event | 6th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1998 - Monterey , United States Duration: 22 Feb 1998 → 25 Feb 1998 https://dl.acm.org/doi/proceedings/10.1145/275107 (Conference proceedings ) |
Publication series
Name | Proceedings of the International Symposium on Field Programmable Gate Arrays, FPGA |
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Conference
Conference | 6th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1998 |
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Country/Territory | United States |
City | Monterey |
Period | 22/02/98 → 25/02/98 |
Internet address |
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Scopus Subject Areas
- Hardware and Architecture
- Electrical and Electronic Engineering