Performance-driven board-level routing for FPGA-based logic emulation (Abstract)

Wai-Kei Mak, D. F. Wong

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

1 Citation (Scopus)

Abstract

In [9] and [10], two algorithms for the board-level routing problem in FPGA-based logic emulators that use crossbars for interconnection were proposed. However, the performance issue was not considered in the previous algorithms. And they cannot handle routing constraints that may arise from certain timing requirement. So, in this paper we propose a performance-driven routing algorithm for the board-level routing problem that can handle additional routing constraints and reduce the delay of the routing solutions.

Original languageEnglish
Title of host publicationFPGA '98
Subtitle of host publicationProceedings of the 1998 ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays
PublisherAssociation for Computing Machinery (ACM)
Pages199-201
Number of pages3
ISBN (Print)9780897919784
DOIs
Publication statusPublished - 22 Feb 1998
Event6th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1998 - Monterey , United States
Duration: 22 Feb 199825 Feb 1998
https://dl.acm.org/doi/proceedings/10.1145/275107 (Conference proceedings )

Publication series

NameProceedings of the International Symposium on Field Programmable Gate Arrays, FPGA

Conference

Conference6th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 1998
Country/TerritoryUnited States
CityMonterey
Period22/02/9825/02/98
Internet address

Scopus Subject Areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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