PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash

Jing Chen; Yi Wang; Amelie Chi Zhou; Rui Mao; Tao Li

doi:10.23919/DATE.2019.8715197

PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash

Jing Chen
, Yi Wang^*
, Amelie Chi Zhou
, Rui Mao^*
, Tao Li

^*Corresponding author for this work

Department of Computer Science

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

10 Citations (Scopus)

Abstract

Advanced three-dimensional (3D) flash memory adopts charge-trap technology that can effectively improve the hit density and reduce the coupling effect. Despite these advantages, 3D charge-trap flash brings a number of new challenges. First, current etching process is unable to manufacture perfect channels with identical feature size. Second, the cell current in 3D charge-trap flash is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D charge-trap flash. This paper presents PATCH, a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. PATCH is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PATCH utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PATCH can effectively enhance the reliability with negligible extra erase operations in comparison with representative schemes.

Original language	English
Title of host publication	Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Publisher	IEEE
Pages	216-221
Number of pages	6
ISBN (Electronic)	9783981926323, 9783981926330
ISBN (Print)	9781728103310
DOIs	https://doi.org/10.23919/DATE.2019.8715197
Publication status	Published - 25 Mar 2019
Event	22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 - Florence, Italy Duration: 25 Mar 2019 → 29 Mar 2019 https://ieeexplore.ieee.org/xpl/conhome/8704855/proceeding (Conference Proceedings)

Publication series

Name	Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE
ISSN (Print)	1530-1591
ISSN (Electronic)	1558-1101

Conference

Conference	22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Country/Territory	Italy
City	Florence
Period	25/03/19 → 29/03/19
Internet address	https://ieeexplore.ieee.org/xpl/conhome/8704855/proceeding (Conference Proceedings)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

User-Defined Keywords

Three-dimensional flash memory
process variation
open-channel SSD
charge-trap flash
space allocation

Access to Document

10.23919/DATE.2019.8715197

Cite this

Chen, J., Wang, Y., Zhou, A. C., Mao, R., & Li, T. (2019). PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash. In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 (pp. 216-221). (Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE). IEEE. https://doi.org/10.23919/DATE.2019.8715197

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title = "PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash",

abstract = "Advanced three-dimensional (3D) flash memory adopts charge-trap technology that can effectively improve the hit density and reduce the coupling effect. Despite these advantages, 3D charge-trap flash brings a number of new challenges. First, current etching process is unable to manufacture perfect channels with identical feature size. Second, the cell current in 3D charge-trap flash is only 20\% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D charge-trap flash. This paper presents PATCH, a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. PATCH is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PATCH utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PATCH can effectively enhance the reliability with negligible extra erase operations in comparison with representative schemes.",

keywords = "Three-dimensional flash memory, process variation, open-channel SSD, charge-trap flash, space allocation",

author = "Jing Chen and Yi Wang and Zhou, \{Amelie Chi\} and Rui Mao and Tao Li",

note = "Publisher Copyright: {\textcopyright} 2019 EDAA. Funding Information: This work was supported in part by the National Natural Science Foundation of China (61502309 and 61802260), in part by the Guangdong Natural Science Foundation (2016A030313045, 2018A030310440, and 2017B030314073), in part by the Shenzhen Science and Technology Foundation (JCYJ20170817100300603, JCYJ20170816093943197, and JCYJ20170302153955969), in part by the Guangdong Pre-national Project (2014GKXM054), in part by the Natural Science Foundation of SZU (803/000027060147), and in part by the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Science (CARCH201608).; 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 ; Conference date: 25-03-2019 Through 29-03-2019",

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Chen, J, Wang, Y, Zhou, AC, Mao, R & Li, T 2019, PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash. in Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE, IEEE, pp. 216-221, 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, Florence, Italy, 25/03/19. https://doi.org/10.23919/DATE.2019.8715197

PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash. / Chen, Jing; Wang, Yi; Zhou, Amelie Chi et al.
Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. IEEE, 2019. p. 216-221 (Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Chen, Jing

AU - Wang, Yi

AU - Zhou, Amelie Chi

AU - Mao, Rui

AU - Li, Tao

N1 - Publisher Copyright: © 2019 EDAA. Funding Information: This work was supported in part by the National Natural Science Foundation of China (61502309 and 61802260), in part by the Guangdong Natural Science Foundation (2016A030313045, 2018A030310440, and 2017B030314073), in part by the Shenzhen Science and Technology Foundation (JCYJ20170817100300603, JCYJ20170816093943197, and JCYJ20170302153955969), in part by the Guangdong Pre-national Project (2014GKXM054), in part by the Natural Science Foundation of SZU (803/000027060147), and in part by the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Science (CARCH201608).

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N2 - Advanced three-dimensional (3D) flash memory adopts charge-trap technology that can effectively improve the hit density and reduce the coupling effect. Despite these advantages, 3D charge-trap flash brings a number of new challenges. First, current etching process is unable to manufacture perfect channels with identical feature size. Second, the cell current in 3D charge-trap flash is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D charge-trap flash. This paper presents PATCH, a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. PATCH is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PATCH utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PATCH can effectively enhance the reliability with negligible extra erase operations in comparison with representative schemes.

AB - Advanced three-dimensional (3D) flash memory adopts charge-trap technology that can effectively improve the hit density and reduce the coupling effect. Despite these advantages, 3D charge-trap flash brings a number of new challenges. First, current etching process is unable to manufacture perfect channels with identical feature size. Second, the cell current in 3D charge-trap flash is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D charge-trap flash. This paper presents PATCH, a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. PATCH is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PATCH utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PATCH can effectively enhance the reliability with negligible extra erase operations in comparison with representative schemes.

KW - Three-dimensional flash memory

KW - process variation

KW - open-channel SSD

KW - charge-trap flash

KW - space allocation

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DO - 10.23919/DATE.2019.8715197

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SN - 9781728103310

T3 - Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE

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BT - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019

PB - IEEE

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ER -

Chen J, Wang Y, Zhou AC, Mao R, Li T. PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash. In Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019. IEEE. 2019. p. 216-221. (Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, DATE). doi: 10.23919/DATE.2019.8715197

PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash

Abstract

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