Optimum Clustering for Delay Minimization

Rajmohan Rajaraman; D. F. Wong

doi:10.1109/43.476579

Optimum Clustering for Delay Minimization

Rajmohan Rajaraman
, D. F. Wong

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Research output: Contribution to journal › Journal article › peer-review

13 Citations (Scopus)

Abstract

This paper addresses the problem of circuit clustering for delay minimization, subject to area capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimum polynomial-time algorithm for combinational circuits under this model. Our algorithm can be generalized to solve the problem under any monotone clustering constraint.

Original language	English
Pages (from-to)	1490-1495
Number of pages	6
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	14
Issue number	12
DOIs	https://doi.org/10.1109/43.476579
Publication status	Published - Dec 1995

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title = "Optimum Clustering for Delay Minimization",

abstract = "This paper addresses the problem of circuit clustering for delay minimization, subject to area capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimum polynomial-time algorithm for combinational circuits under this model. Our algorithm can be generalized to solve the problem under any monotone clustering constraint.",

author = "Rajmohan Rajaraman and Wong, \{D. F.\}",

note = "Funding Information: This work was supported in part by the Texas Advanced Research Program under grant 003658459 and in part from an MCD Fellowship from the University of Texas at Austin. Publisher Copyright: {\textcopyright} 1995 IEEE ",

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AU - Rajaraman, Rajmohan

AU - Wong, D. F.

N1 - Funding Information: This work was supported in part by the Texas Advanced Research Program under grant 003658459 and in part from an MCD Fellowship from the University of Texas at Austin. Publisher Copyright: © 1995 IEEE

PY - 1995/12

Y1 - 1995/12

N2 - This paper addresses the problem of circuit clustering for delay minimization, subject to area capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimum polynomial-time algorithm for combinational circuits under this model. Our algorithm can be generalized to solve the problem under any monotone clustering constraint.

AB - This paper addresses the problem of circuit clustering for delay minimization, subject to area capacity constraints. We use the general delay model, for which only heuristic solutions were known. We present an optimum polynomial-time algorithm for combinational circuits under this model. Our algorithm can be generalized to solve the problem under any monotone clustering constraint.

UR - https://www.scopus.com/pages/publications/0029491236

U2 - 10.1109/43.476579

DO - 10.1109/43.476579

M3 - Journal article

AN - SCOPUS:0029491236

SN - 0278-0070

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JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 12

ER -

Optimum Clustering for Delay Minimization

Abstract

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