Optimization of standard cell based detailed placement for 16 nm FinFET process

Keyphrases

• Detailed Placement 100%
• Standard Cell-based 100%
• Fin Field-effect Transistor (FinFET) 100%
• Dummy Gate 100%
• Adjacent Cell 100%
• Source Node 75%
• Cell Boundary 50%
• High Performance 25%
• Graph Model 25%
• Foundry 25%
• Device Degradation 25%
• Congestion 25%
• Optimization Strategy 25%
• Transistor 25%
• Edge Devices 25%
• Design Rules 25%
• Node Insertion 25%
• Placement Optimization 25%
• Device Edge 25%
• Global Placement 25%
• Technology Node 25%
• Standard Cell Placement 25%
• Standard-cell-based Design 25%
• Semiconductor Device Manufacture 25%
• Low Power Applications 25%
• Planar MOSFET 25%
• Parasitic Transistor 25%
• Power Rail 25%
• Drain-to-drain Abutment 25%

Engineering

• Adjacent Cell 100%
• Source Node 75%
• Nodes 50%
• Experimental Result 25%
• Optimization Strategy 25%
• Design Rule 25%
• Abutment 25%
• Power Rail 25%
• Metal-Oxide-Semiconductor Field-Effect Transistor 25%
• Field Effect Transistor 25%
• Semiconductor Device Fabrication 25%

Computer Science

• Detailed Placement 100%
• Experimental Result 33%
• Optimization Strategy 33%
• Global Placement 33%