Optimal module implementation and its application to transistor placement

T.W. Her; D.F. Wong

doi:10.1109/ICCAD.1991.185202

Optimal module implementation and its application to transistor placement

T.W. Her, D.F. Wong

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Abstract

The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.

Original language	English
Title of host publication	1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
Publisher	IEEE
Pages	98-101
Number of pages	4
ISBN (Print)	0818621575
DOIs	https://doi.org/10.1109/ICCAD.1991.185202
Publication status	Published - 14 Nov 1991
Event	1991 IEEE International Conference on Computer-Aided Design, ICCAD 1991 - Santa Clara, United States Duration: 11 Nov 1991 → 14 Nov 1991 https://ieeexplore.ieee.org/xpl/conhome/345/proceeding

Publication series

Name	IEEE International Conference on Computer-Aided Design, ICCAD

Conference

Conference	1991 IEEE International Conference on Computer-Aided Design, ICCAD 1991
Country/Territory	United States
City	Santa Clara
Period	11/11/91 → 14/11/91
Internet address	https://ieeexplore.ieee.org/xpl/conhome/345/proceeding

User-Defined Keywords

Application software
Satellites
Benchmark testing
Very large scale integration
Shape
Density measurement

Access to Document

10.1109/ICCAD.1991.185202

Cite this

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title = "Optimal module implementation and its application to transistor placement",

abstract = "The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.",

keywords = "Application software, Satellites, Benchmark testing, Very large scale integration, Shape, Density measurement",

author = "T.W. Her and D.F. Wong",

note = "This work was partially supported by the National Science Foundation under grant MIP-8909586 and by an IBM Faculty Development Award.; 1991 IEEE International Conference on Computer-Aided Design, ICCAD 1991 ; Conference date: 11-11-1991 Through 14-11-1991",

year = "1991",

month = nov,

day = "14",

doi = "10.1109/ICCAD.1991.185202",

language = "English",

isbn = "0818621575",

series = "IEEE International Conference on Computer-Aided Design, ICCAD",

publisher = "IEEE",

pages = "98--101",

booktitle = "1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers",

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url = "https://ieeexplore.ieee.org/xpl/conhome/345/proceeding",

}

Her, TW & Wong, DF 1991, Optimal module implementation and its application to transistor placement. in 1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. IEEE International Conference on Computer-Aided Design, ICCAD, IEEE, pp. 98-101, 1991 IEEE International Conference on Computer-Aided Design, ICCAD 1991, Santa Clara, California, United States, 11/11/91. https://doi.org/10.1109/ICCAD.1991.185202

TY - GEN

T1 - Optimal module implementation and its application to transistor placement

AU - Her, T.W.

AU - Wong, D.F.

N1 - This work was partially supported by the National Science Foundation under grant MIP-8909586 and by an IBM Faculty Development Award.

PY - 1991/11/14

Y1 - 1991/11/14

N2 - The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.

AB - The authors present an algorithm for selecting implementations for rectangular modules given a placement of the modules in multiple rows. A module is a rectangle with terminals located on the top and the bottom edges. An implementation of a module is specified by its dimension and a placement of the terminals along the top and bottom edges of the module. The algorithm accepts as input a placement of the modules and a set of possible implementations of each module, and selects an implementation for each module to minimize the total height of the layout. The time complexity of the algorithm is specified. The authors also present two extensions of the algorithm. The algorithm can be applied to CMOS transistor placement and has been implemented in the custom cell synthesis system of the MCC Physical Satellite. The algorithm was tested on cells selected from the MCNC benchmarks and industry, and reductions of up to 19% in layout area were obtained.

KW - Application software

KW - Satellites

KW - Benchmark testing

KW - Very large scale integration

KW - Shape

KW - Density measurement

UR - https://ieeexplore.ieee.org/document/185202/

U2 - 10.1109/ICCAD.1991.185202

DO - 10.1109/ICCAD.1991.185202

M3 - Conference proceeding

SN - 0818621575

T3 - IEEE International Conference on Computer-Aided Design, ICCAD

SP - 98

EP - 101

BT - 1991 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

PB - IEEE

T2 - 1991 IEEE International Conference on Computer-Aided Design, ICCAD 1991

Y2 - 11 November 1991 through 14 November 1991

ER -

Optimal module implementation and its application to transistor placement

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