Optimal low power XOR gate decomposition

Hai Zhou, D. F. Wong

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

17 Citations (Scopus)


With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. For the problem of low power decomposition of an XOR gate, if the implementation technology is static CMOS logic, previous research gave an O(n) log (n) time algorithm which assumes that the inputs have both polarities available. But that approach can not be used in dynamic logic. In this paper, we analyze the properties of optimal XOR decompositions in dynamic logic. Based on these optimality properties, we design an optimal algorithm to solve the low power XOR decomposition problem in dynamic logic. We also point out that the previous solution for static logic is not optimal, and give an optimal algorithm which does not even change the input polarities.
Original languageEnglish
Title of host publication37th ACM/IEEE Design Automation Conference - Proceedings 2000
PublisherAssociation for Computing Machinery (ACM)
Number of pages4
ISBN (Print)9781581131871, 1581131879
Publication statusPublished - 5 Jun 2000
Event37th ACM/IEEE-CAS/EDAC Design Automation Conference, DAC 2000 - Los Angeles, United States
Duration: 5 Jun 20009 Jun 2000
https://dl.acm.org/doi/proceedings/10.1145/337292 (Conference proceedings)
https://ieeexplore.ieee.org/xpl/conhome/6899/proceeding (Conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference37th ACM/IEEE-CAS/EDAC Design Automation Conference, DAC 2000
Country/TerritoryUnited States
CityLos Angeles
Internet address


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