Optimal algorithm for minimizing the number of twists in an on-chip bus

Keyphrases

• Coupled Noise 100%
• Optimal Algorithm 100%
• On-chip Bus 100%
• Engineering Change Order 100%
• Bus Architecture 66%
• Minimum number 33%
• Low Power 33%
• Layout Change 33%
• Circuit Design 33%
• Design Flow 33%
• Deep Submicron 33%
• Noise Constraint 33%
• Chip Design 33%
• Bus Structure 33%
• Speed-power 33%
• Improvement Requirements 33%
• Shortest Path Algorithm 33%
• VLSI chip 33%
• Twisted Wire 33%
• Capacitive Coupling 33%

Computer Science

• Experimental Result 100%
• Optimal Algorithm 100%
• Capacitive Coupling 100%
• Shortest Path Algorithm 100%

Engineering

• Engineering 100%
• Experimental Result 33%
• Circuit Design 33%
• Crosstalk 33%
• Design Flow 33%
• Capacitive Coupling 33%