On timing closure: Buffer insertion for hold-violation removal

Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

16 Citations (Scopus)

Abstract

Timing closure, which is to meet the design's timing constraints, is a key problem in the physical design flow. During the timing optimization process, buffers can be used to speedup the circuit or serve as delay elements. In this paper, we study the hold-violation removal problem for today's industrial designs. Discrete buffers, accurate timing models/analysis, and complex timing constraints make the problem difficult and time-consuming to solve. In this paper, we first present a linear programming-based methodology to model the setup and hold-time constraints. Then based on the solution to the linear programming, buffers are inserted as delay elements to solve hold violations. In the experiment, our approach is tested on industrial designs, then runs with the industrial optimization flow, and better results in terms of hold violations and runtime are reported.
Original languageEnglish
Title of host publication51st ACM/IEEE Design Automation Conference 2014
PublisherAssociation for Computing Machinery (ACM)
Pages1-6
Number of pages6
ISBN (Electronic)9781450327305
DOIs
Publication statusPublished - Jun 2014
Event51st ACM/EDAC/IEEE Design Automation Conference, DAC 2014 - San Francisco, United States
Duration: 1 Jun 20145 Jun 2014
https://dl.acm.org/doi/proceedings/10.1145/2593069 (Conference proceedings)
https://ieeexplore.ieee.org/xpl/conhome/6877791/proceeding (Conference proceedings)

Publication series

NameProceedings of ACM/IEEE Design Automation Conference

Conference

Conference51st ACM/EDAC/IEEE Design Automation Conference, DAC 2014
Country/TerritoryUnited States
CitySan Francisco
Period1/06/145/06/14
Internet address

User-Defined Keywords

  • Timing optimization
  • physical synthesis
  • buffer insertion

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