The structural tree-based mapping algorithm is an efficient and popular technique for technology mapping. In order to make good use of this mapping technique, it is desirable to design FPGA logic modules based on Boolean functions which can be represented by a tree of gates (i.e. series-parallel or SP functions). In , the authors studied this issue and demonstrated the advantages of designing logic modules as universal SP functions, i.e. SP functions which can implement all SP functions with a certain number of inputs. However, the universal SP functions presented in  were designed manually and an automatic generation of universal SP functions was left as an open problem. In this paper, we present an algorithm to generate, for each n>0, a universal SP function for implementing all n-input SP functions. We also present an efficient Boolean matching algorithm for matching functions to the universal SP functions that we constructed. As it is important to have alternative universal SP functions from which logic-module designers can choose a design taking other criteria (e.g. area, delay, or power) into consideration, we developed an algorithm to generate alternative universal SP functions. In particular, we have found all universal SP functions for n-input SP functions, when n≤6.