Skip to main navigation
Skip to search
Skip to main content
Hong Kong Baptist University Home
Help & FAQ
Home
Scholars
Departments / Units
Research Output
Projects / Grants
Prizes / Awards
Activities
Press/Media
Student theses
Datasets
Search by expertise, name or affiliation
On retiming for FPGA logic module minimization
Y.P. Chen,
D.F. Wong
Office of the Provost
Research output
:
Contribution to journal
›
Journal article
›
peer-review
Overview
Fingerprint
Fingerprint
Dive into the research topics of 'On retiming for FPGA logic module minimization'. Together they form a unique fingerprint.
Sort by:
Weight
Alphabetically
Keyphrases
Combinational
100%
Logic Module
100%
Module Minimization
100%
Retiming
100%
Integer Programming
66%
Flip-flop
66%
Minimization Problem
33%
Constraint Matrix
33%
Linear Programming Relaxation
33%
Integer Linear Programming
33%
Totally Unimodular
33%
Sequential Circuits
33%
Retiming Technique
33%
Computer Science
Integer Program
100%
Field Programmable Gate Array
100%
Minimization Problem
50%
Linear Program
50%
Sequential Circuit
50%
Mathematics
Integer
100%
Minimizes
33%
Minimization Problem
33%
Matrix (Mathematics)
33%
Linear Program
33%