On retiming for FPGA logic module minimization

Y. P. Chen; D. F. Wong

doi:10.1109/ICCD.1994.331934

On retiming for FPGA logic module minimization

Y. P. Chen^*, D. F. Wong

^*Corresponding author for this work

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

1 Citation (Scopus)

Abstract

In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.

Original language	English
Title of host publication	1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors
Publisher	IEEE
Pages	394-397
Number of pages	4
ISBN (Print)	0818665653
DOIs	https://doi.org/10.1109/ICCD.1994.331934
Publication status	Published - Oct 1994
Event	1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors - Cambridge, United States Duration: 10 Oct 1994 → 12 Oct 1994 https://ieeexplore.ieee.org/xpl/conhome/1002/proceeding (Link to conference proceedings)

Publication series

Name	Proceedings of 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors

Conference

Conference	1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors
Country/Territory	United States
City	Cambridge
Period	10/10/94 → 12/10/94
Internet address	https://ieeexplore.ieee.org/xpl/conhome/1002/proceeding (Link to conference proceedings)

Scopus Subject Areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICCD.1994.331934

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title = "On retiming for FPGA logic module minimization",

abstract = "In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.",

author = "Chen, {Y. P.} and Wong, {D. F.}",

note = "Funding Information: *This work was partially supported by the Texas Advanced Research Program under Grant No.003658459 and by a DAC Design Automation Scholarship. Publisher Copyright: {\textcopyright} 1994 IEEE; 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors ; Conference date: 10-10-1994 Through 12-10-1994",

year = "1994",

month = oct,

doi = "10.1109/ICCD.1994.331934",

language = "English",

isbn = "0818665653",

series = "Proceedings of 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors",

publisher = "IEEE",

pages = "394--397",

booktitle = "1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/1002/proceeding",

}

Chen, YP & Wong, DF 1994, On retiming for FPGA logic module minimization. in 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors. Proceedings of 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors, IEEE, pp. 394-397, 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors, Cambridge, Massachusetts, United States, 10/10/94. https://doi.org/10.1109/ICCD.1994.331934

On retiming for FPGA logic module minimization. / Chen, Y. P.; Wong, D. F.
1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors. IEEE, 1994. p. 394-397 (Proceedings of 1994 IEEE International Conference on Computer Design, ICCD 1994: VLSI in Computers and Processors).

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

TY - CHAP

T1 - On retiming for FPGA logic module minimization

AU - Chen, Y. P.

AU - Wong, D. F.

N1 - Funding Information: *This work was partially supported by the Texas Advanced Research Program under Grant No.003658459 and by a DAC Design Automation Scholarship. Publisher Copyright: © 1994 IEEE

PY - 1994/10

Y1 - 1994/10

N2 - In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.

AB - In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that can not be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.

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On retiming for FPGA logic module minimization

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