On retiming for FPGA logic module minimization

Y.P. Chen, D.F. Wong

Research output: Contribution to journalJournal articlepeer-review

Abstract

In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a flip-flop is the only destination of its driving combinational block, then both the flip-flop and the combinational block can be put in a sequential module. Retiming technique is applied to minimize the number of registers that cannot be merged with combinational blocks. We formulate the problem as an integer linear program. We show that the constraint matrix of the integer program is totally unimodular. As a result, we can solve our logic module minimization problem optimally by solving the linear relaxation of the integer program.

Original languageEnglish
Pages (from-to)135-145
Number of pages11
JournalIntegration, the VLSI Journal
Volume24
Issue number2
DOIs
Publication statusPublished - Dec 1997

Scopus Subject Areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

User-Defined Keywords

  • FPGA
  • Linear program
  • Logic module
  • Retiming

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