On process-aware 1-D standard cell design

Hongbo Zhang; Martin D. F. Wong; Kai Yuan Chao

doi:10.1109/ASPDAC.2010.5419686

On process-aware 1-D standard cell design

Hongbo Zhang, Martin D. F. Wong, Kai Yuan Chao

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

19 Citations (Scopus)

Abstract

When VLSI technology scales down to sub-40nm process node, systematic variation introduced by the lithography is a persistent challenge to the manufacturability. The limitation of the resolution enhancement technologies (RETs) forces people to adopt a regular cell design methodology. In this paper, targeted on 1-D cell design, we use simulation data to analyze the relationship between the line-end gap distribution and printability. Based on the gap distribution preferences, an optimal algorithm is provided to efficiently extend the line ends and insert dummies, which will significantly improve the gap distribution and help printability. Experimental results on 45nm and 32nm processes show that significant improvement can be obtained on edge placement error (EPE).

Original language	English
Title of host publication	Proceedings of The 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Publisher	IEEE
Pages	838-842
Number of pages	5
ISBN (Print)	9781424457656
DOIs	https://doi.org/10.1109/ASPDAC.2010.5419686
Publication status	Published - 21 Jan 2010
Event	15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei International Convention Center, Taipei, Taiwan, Province of China Duration: 18 Jan 2010 → 21 Jan 2010 https://www.aspdac.com/aspdac2010/ (Conference website) https://www.aspdac.com/aspdac2010/pdf/ASP-DAC%202010%20Advance%20Program%20Final1215.pdf (Conference programme) https://ieeexplore.ieee.org/xpl/conhome/5415928/proceeding (Conference proceedings)

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DACPapers, ICCAD
ISSN (Print)	2153-6961
ISSN (Electronic)	2153-697X

Conference

Conference	15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Country/Territory	Taiwan, Province of China
City	Taipei
Period	18/01/10 → 21/01/10
Internet address	https://www.aspdac.com/aspdac2010/ (Conference website) https://www.aspdac.com/aspdac2010/pdf/ASP-DAC%202010%20Advance%20Program%20Final1215.pdf (Conference programme) https://ieeexplore.ieee.org/xpl/conhome/5415928/proceeding (Conference proceedings)

Scopus Subject Areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2010.5419686

Cite this

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title = "On process-aware 1-D standard cell design",

abstract = "When VLSI technology scales down to sub-40nm process node, systematic variation introduced by the lithography is a persistent challenge to the manufacturability. The limitation of the resolution enhancement technologies (RETs) forces people to adopt a regular cell design methodology. In this paper, targeted on 1-D cell design, we use simulation data to analyze the relationship between the line-end gap distribution and printability. Based on the gap distribution preferences, an optimal algorithm is provided to efficiently extend the line ends and insert dummies, which will significantly improve the gap distribution and help printability. Experimental results on 45nm and 32nm processes show that significant improvement can be obtained on edge placement error (EPE).",

author = "Hongbo Zhang and Wong, {Martin D. F.} and Chao, {Kai Yuan}",

note = "This work was partially supported by the National Science Foundation under grant CCF-0701821 and a grant from the Semiconductor Research Corporation (SRC).; 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 ; Conference date: 18-01-2010 Through 21-01-2010",

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booktitle = "Proceedings of The 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010",

address = "United States",

url = "https://www.aspdac.com/aspdac2010/, https://www.aspdac.com/aspdac2010/pdf/ASP-DAC%202010%20Advance%20Program%20Final1215.pdf, https://ieeexplore.ieee.org/xpl/conhome/5415928/proceeding",

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Zhang, H, Wong, MDF & Chao, KY 2010, On process-aware 1-D standard cell design. in Proceedings of The 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DACPapers, ICCAD, IEEE, pp. 838-842, 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, Province of China, 18/01/10. https://doi.org/10.1109/ASPDAC.2010.5419686

On process-aware 1-D standard cell design. / Zhang, Hongbo; Wong, Martin D. F.; Chao, Kai Yuan.
Proceedings of The 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. IEEE, 2010. p. 838-842 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DACPapers, ICCAD).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AB - When VLSI technology scales down to sub-40nm process node, systematic variation introduced by the lithography is a persistent challenge to the manufacturability. The limitation of the resolution enhancement technologies (RETs) forces people to adopt a regular cell design methodology. In this paper, targeted on 1-D cell design, we use simulation data to analyze the relationship between the line-end gap distribution and printability. Based on the gap distribution preferences, an optimal algorithm is provided to efficiently extend the line ends and insert dummies, which will significantly improve the gap distribution and help printability. Experimental results on 45nm and 32nm processes show that significant improvement can be obtained on edge placement error (EPE).

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On process-aware 1-D standard cell design

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