In this paper, we consider a board-level routing problem which is applicable to field-programmable gate arrays (FPGA)-based logic emulation systems such as the Realizer System  and the Enterprise Emulation System  manufactured by Quickturn Design Systems. For the case where all nets are two-terminal nets, we present an O(n2)-time optimal algorithm where n is the number of nets. Our algorithm guarantees 100% routing completion if the number of interchip signal pins on each FPGA chip in the logic emulation system is less than or equal to the number of I/O pins on the chip. Our algorithm is based on iterative computation of Euler circuits in graphs. We also prove that the routing problem with multiterminal nets is NP-complete. And we suggest one way to handle multiterminal nets using some additional resources.
|Number of pages
|IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|Published - Mar 1997
Scopus Subject Areas
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering