On fast timing closure: speeding up incremental path-based timing analysis with mapreduce

Tsung-wei Huang; Martin D. F. Wong

doi:10.1109/SLIP.2015.7171710

On fast timing closure: speeding up incremental path-based timing analysis with mapreduce

Tsung-wei Huang
, Martin D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

4 Citations (Scopus)

Abstract

Incremental path-based timing analysis (PBA) is a pivotal step in the timing optimization flow. A core building block analyzes the timing path-by-path subject to a critical amount of incremental changes on the design. However, this process in nature demands an extremely high computational complexity and has been a major bottleneck in accelerating timing closure. Therefore, we introduce in this paper a fast and scalable algorithm of incremental PBA with MapReduce – a recently popular programming paradigm in big-data era. Inspired by the spirit of MapReduce, we formulate our problem into tasks that are associated with keys and values and perform massively-parallel map and reduce operations on a distributed system. Experimental results demonstrated that our approach can not only easily analyze huge deisgns in a few minutes, but also quickly revalidate the timing after the incremental changes. Our results are beneficial for speeding up the lengthy design cycle of timing closure.

Original language	English
Title of host publication	2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781467381895
DOIs	https://doi.org/10.1109/SLIP.2015.7171710
Publication status	Published - Jun 2015
Event	2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) - San Francisco, United States Duration: 6 Jun 2015 → 6 Jun 2015 https://ieeexplore.ieee.org/xpl/conhome/7160953/proceeding (Link to conference proceedings)

Publication series

Name	Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

Conference

Conference	2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Country/Territory	United States
City	San Francisco
Period	6/06/15 → 6/06/15
Internet address	https://ieeexplore.ieee.org/xpl/conhome/7160953/proceeding (Link to conference proceedings)

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10.1109/SLIP.2015.7171710

Cite this

Huang, T., & Wong, M. D. F. (2015). On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. In 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) (pp. 1-6). Article 7171710 (Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)). IEEE. https://doi.org/10.1109/SLIP.2015.7171710

@inproceedings{dd8fa627967048488efafee06c48fb15,

title = "On fast timing closure: speeding up incremental path-based timing analysis with mapreduce",

abstract = "Incremental path-based timing analysis (PBA) is a pivotal step in the timing optimization flow. A core building block analyzes the timing path-by-path subject to a critical amount of incremental changes on the design. However, this process in nature demands an extremely high computational complexity and has been a major bottleneck in accelerating timing closure. Therefore, we introduce in this paper a fast and scalable algorithm of incremental PBA with MapReduce – a recently popular programming paradigm in big-data era. Inspired by the spirit of MapReduce, we formulate our problem into tasks that are associated with keys and values and perform massively-parallel map and reduce operations on a distributed system. Experimental results demonstrated that our approach can not only easily analyze huge deisgns in a few minutes, but also quickly revalidate the timing after the incremental changes. Our results are beneficial for speeding up the lengthy design cycle of timing closure.",

author = "Tsung-wei Huang and Wong, \{Martin D. F.\}",

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doi = "10.1109/SLIP.2015.7171710",

language = "English",

series = "Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)",

publisher = "IEEE",

pages = "1--6",

booktitle = "2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)",

address = "United States",

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}

Huang, T & Wong, MDF 2015, On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. in 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)., 7171710, Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), IEEE, pp. 1-6, 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), San Francisco, California, United States, 6/06/15. https://doi.org/10.1109/SLIP.2015.7171710

On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. / Huang, Tsung-wei; Wong, Martin D. F.
2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP). IEEE, 2015. p. 1-6 7171710 (Proceedings of ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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On fast timing closure: speeding up incremental path-based timing analysis with mapreduce

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