Multiplexor network generation in high level synthesis

Yung-Ming Fang; D. F. Wong

doi:10.1109/ICCD.1996.563537

Multiplexor network generation in high level synthesis

Yung-Ming Fang, D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

Abstract

In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper, we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our approach obtains 8 to 25% improvement over a direct multiplexor-forest approach.

Original language	English
Title of host publication	1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors
Publisher	IEEE
Pages	78-83
Number of pages	6
ISBN (Print)	0818675543
DOIs	https://doi.org/10.1109/ICCD.1996.563537
Publication status	Published - Oct 1996
Event	1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors - Austin, United States Duration: 7 Oct 1996 → 9 Oct 1996 https://ieeexplore.ieee.org/xpl/conhome/4128/proceeding (Link to conference proceedings)

Publication series

Name	Proceedings of 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors

Conference

Conference	1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors
Country/Territory	United States
City	Austin
Period	7/10/96 → 9/10/96
Internet address	https://ieeexplore.ieee.org/xpl/conhome/4128/proceeding (Link to conference proceedings)

Access to Document

10.1109/ICCD.1996.563537

Cite this

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title = "Multiplexor network generation in high level synthesis",

abstract = "In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper, we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our approach obtains 8 to 25% improvement over a direct multiplexor-forest approach.",

author = "Yung-Ming Fang and Wong, {D. F.}",

note = "Publisher Copyright: {\textcopyright} 1996 IEEE ; 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors ; Conference date: 07-10-1996 Through 09-10-1996",

year = "1996",

month = oct,

doi = "10.1109/ICCD.1996.563537",

language = "English",

isbn = "0818675543",

series = "Proceedings of 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors",

publisher = "IEEE",

pages = "78--83",

booktitle = "1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/4128/proceeding",

}

Fang, Y-M & Wong, DF 1996, Multiplexor network generation in high level synthesis. in 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors. Proceedings of 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors, IEEE, pp. 78-83, 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors, Austin, California, United States, 7/10/96. https://doi.org/10.1109/ICCD.1996.563537

Multiplexor network generation in high level synthesis. / Fang, Yung-Ming; Wong, D. F.
1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors. IEEE, 1996. p. 78-83 (Proceedings of 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors).

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

TY - CHAP

T1 - Multiplexor network generation in high level synthesis

AU - Fang, Yung-Ming

AU - Wong, D. F.

PY - 1996/10

Y1 - 1996/10

N2 - In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper, we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our approach obtains 8 to 25% improvement over a direct multiplexor-forest approach.

AB - In high level synthesis, after the binding stage, multiplexor network is generated to connect the outputs of modules (functional-units/registers) to the inputs of modules. In this paper, we present an algorithm to generate a 2-to-1 multiplexor network with minimum number of multiplexors. Our algorithm is based on iteratively solving minimum vertex cover problems. Experimental results show that our approach obtains 8 to 25% improvement over a direct multiplexor-forest approach.

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U2 - 10.1109/ICCD.1996.563537

DO - 10.1109/ICCD.1996.563537

M3 - Chapter

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T3 - Proceedings of 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors

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BT - 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors

PB - IEEE

T2 - 1996 International Conference on Computer Design, ICCD 1996: VLSI in Computers and Processors

Y2 - 7 October 1996 through 9 October 1996

ER -

Multiplexor network generation in high level synthesis

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