Maximum Fanout-Free Window Enumeration: Towards Multi-Output Sub-Structure Synthesis

Ruofei Tang, Xuliang Zhu, Lei Chen*, Xing Li, Xin Huang, Mingxuan Yuan, Jianliang Xu

*Corresponding author for this work

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

Abstract

Peephole optimization is commonly used in And-Inverter Graphs (AIGs) optimization algorithms. The efficiency of these algorithms heavily relies on the enumeration process of sub-structures. One common sub-structure is the cut, known for its efficient enumeration method and single-output characteristic. However, an increasing number of optimization algorithms now target sub-structures that incorporate multiple outputs. In this paper, we explore Maximum Fanout-Free Windows (MFFWs), a novel sub-structure with a multi-output nature, as well as its practical applications and enumeration algorithms. To accommodate various algorithm execution processes, we propose two different enumeration styles: Dynamic and Static. The Dynamic approach provides flexibility in adapting to changes in the AIG structure, whereas the Static method ensures efficiency as long as the AIG structure remains unchanged during execution. We apply these methods to rewriting and technology mapping to improve their runtime performance. Experimental results on pure enumeration and practical scenarios show the scalability and efficiency of the proposed MFFW enumeration methods.
Original languageEnglish
Title of host publication2025 Design, Automation & Test in Europe Conference (DATE)
PublisherIEEE
Pages1-7
Number of pages7
ISBN (Electronic)9783982674100
ISBN (Print)9798331534646
DOIs
Publication statusPublished - 31 Mar 2025
Event2025 Design, Automation and Test in Europe Conference, DATE 2025 - Lyon, France
Duration: 31 Mar 20252 Apr 2025
https://ieeexplore.ieee.org/xpl/conhome/10992638/proceeding

Publication series

NameProceedings - Design, Automation, and Test in Europe Conference and Exhibition
PublisherIEEE
ISSN (Print)1530-1591
ISSN (Electronic)1558-1101

Conference

Conference2025 Design, Automation and Test in Europe Conference, DATE 2025
Country/TerritoryFrance
CityLyon
Period31/03/252/04/25
Internet address

User-Defined Keywords

  • And-Inverter Graph
  • Combinational circuits
  • Cut
  • Europe
  • Heuristic algorithms
  • Logic
  • Logic Optimization
  • Logic Synthesis
  • Optimization
  • Runtime
  • Scalability
  • Time complexity

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