Abstract
Peephole optimization is commonly used in And-Inverter Graphs (AIGs) optimization algorithms. The efficiency of these algorithms heavily relies on the enumeration process of sub-structures. One common sub-structure is the cut, known for its efficient enumeration method and single-output characteristic. However, an increasing number of optimization algorithms now target sub-structures that incorporate multiple outputs. In this paper, we explore Maximum Fanout-Free Windows (MFFWs), a novel sub-structure with a multi-output nature, as well as its practical applications and enumeration algorithms. To accommodate various algorithm execution processes, we propose two different enumeration styles: Dynamic and Static. The Dynamic approach provides flexibility in adapting to changes in the AIG structure, whereas the Static method ensures efficiency as long as the AIG structure remains unchanged during execution. We apply these methods to rewriting and technology mapping to improve their runtime performance. Experimental results on pure enumeration and practical scenarios show the scalability and efficiency of the proposed MFFW enumeration methods.
Original language | English |
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Title of host publication | 2025 Design, Automation & Test in Europe Conference (DATE) |
Publisher | IEEE |
Pages | 1-7 |
Number of pages | 7 |
ISBN (Electronic) | 9783982674100 |
ISBN (Print) | 9798331534646 |
DOIs | |
Publication status | Published - 31 Mar 2025 |
Event | 2025 Design, Automation and Test in Europe Conference, DATE 2025 - Lyon, France Duration: 31 Mar 2025 → 2 Apr 2025 https://ieeexplore.ieee.org/xpl/conhome/10992638/proceeding |
Publication series
Name | Proceedings - Design, Automation, and Test in Europe Conference and Exhibition |
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Publisher | IEEE |
ISSN (Print) | 1530-1591 |
ISSN (Electronic) | 1558-1101 |
Conference
Conference | 2025 Design, Automation and Test in Europe Conference, DATE 2025 |
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Country/Territory | France |
City | Lyon |
Period | 31/03/25 → 2/04/25 |
Internet address |
User-Defined Keywords
- And-Inverter Graph
- Combinational circuits
- Cut
- Europe
- Heuristic algorithms
- Logic
- Logic Optimization
- Logic Synthesis
- Optimization
- Runtime
- Scalability
- Time complexity