Mask cost reduction with circuit performance consideration for self-aligned double patterning

Keyphrases

• Cost Reduction 100%
• Mask Cost 100%
• Self-aligned Double Patterning 100%
• Circuit Performance 100%
• Performance Considerations 100%
• Double Patterning Lithography 60%
• Double Exposure 60%
• Cut Mask 60%
• Polygon 40%
• Double Patterning 40%
• Reduction Method 20%
• Decomposition Problem 20%
• Graph Coloring 20%
• Impact Performance 20%
• Manufacturing Cost 20%
• Layout Decomposition 20%
• Design Perspective 20%
• Overlay Error 20%
• 1D Design 20%
• 2D Features 20%
• Trim-Away 20%
• Lithography Technology 20%
• Constrained Shortest Path Problem 20%
• 32nm Node 20%

Engineering

• Cost Reduction 100%
• Lithography 100%
• Circuit Performance 100%
• Experimental Result 33%
• Nodes 33%
• Simplifies 33%
• Enabling Technology 33%
• Manufacturing Cost 33%

Material Science

• Electronic Circuit 100%
• Lithography 100%