Manufacturability-aware physical layout optimizations

David Z. Pan; Martin D.F. Wong

doi:10.1109/icicdt.2005.1502616

Manufacturability-aware physical layout optimizations

David Z. Pan^*, Martin D.F. Wong

^*Corresponding author for this work

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

8 Citations (Scopus)

Abstract

Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.

Original language	English
Title of host publication	2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Publisher	IEEE
Pages	149-153
Number of pages	5
ISBN (Print)	0780390814, 9780780390812
DOIs	https://doi.org/10.1109/icicdt.2005.1502616
Publication status	Published - May 2005
Event	2005 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, United States Duration: 9 May 2005 → 11 May 2005 https://ieeexplore.ieee.org/xpl/conhome/10047/proceeding

Publication series

Name	International Conference on Integrated Circuit Design and Technology, ICICDT
ISSN (Print)	2381-3555

Conference

Conference	2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Country/Territory	United States
City	Austin
Period	9/05/05 → 11/05/05
Internet address	https://ieeexplore.ieee.org/xpl/conhome/10047/proceeding

Scopus Subject Areas

General Engineering

Access to Document

10.1109/icicdt.2005.1502616

Cite this

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title = "Manufacturability-aware physical layout optimizations",

abstract = "Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.",

author = "Pan, {David Z.} and Wong, {Martin D.F.}",

note = "Funding Information: This work was partially supported by an IBM Faculty Award National Science Foundation under grant CCR-0306244, an Intel Equipment Grant, and the lithography simulation software donations from KLA-Tencor and Sigma-C. Publisher copyright: {\textcopyright} 2005 IEEE; 2005 International Conference on Integrated Circuit Design and Technology, ICICDT ; Conference date: 09-05-2005 Through 11-05-2005",

year = "2005",

month = may,

doi = "10.1109/icicdt.2005.1502616",

language = "English",

isbn = "0780390814",

series = "International Conference on Integrated Circuit Design and Technology, ICICDT",

publisher = "IEEE",

pages = "149--153",

booktitle = "2005 International Conference on Integrated Circuit Design and Technology, ICICDT",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/10047/proceeding",

}

Pan, DZ & Wong, MDF 2005, Manufacturability-aware physical layout optimizations. in 2005 International Conference on Integrated Circuit Design and Technology, ICICDT. International Conference on Integrated Circuit Design and Technology, ICICDT, IEEE, pp. 149-153, 2005 International Conference on Integrated Circuit Design and Technology, ICICDT, Austin, Texas, United States, 9/05/05. https://doi.org/10.1109/icicdt.2005.1502616

Manufacturability-aware physical layout optimizations. / Pan, David Z.; Wong, Martin D.F.
2005 International Conference on Integrated Circuit Design and Technology, ICICDT. IEEE, 2005. p. 149-153 (International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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N1 - Funding Information: This work was partially supported by an IBM Faculty Award National Science Foundation under grant CCR-0306244, an Intel Equipment Grant, and the lithography simulation software donations from KLA-Tencor and Sigma-C. Publisher copyright: © 2005 IEEE

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N2 - Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.

AB - Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.

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ER -

Manufacturability-aware physical layout optimizations

Abstract

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Scopus Subject Areas

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