Manufacturability-aware physical layout optimizations

David Z. Pan*, Martin D.F. Wong

*Corresponding author for this work

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

8 Citations (Scopus)

Abstract

Nanometer VLSI design is greatly challanged by the growing interdependency between manufacturing and design. Existing approaches in design for manufacturability (DFM) are still mostly post design, rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper manufacturing metrics and cost functions upstream, especially at the key physical layout optimization stages such as routing and placement, to have major impacts. In this paper, we show several aspects of the true manufactruability-aware physical design, from lithography-aware routing, to redundant-via aware routing, to CMP aware florplanning and placement, and show their promises.

Original languageEnglish
Title of host publication2005 International Conference on Integrated Circuit Design and Technology, ICICDT
PublisherIEEE
Pages149-153
Number of pages5
ISBN (Print)0780390814, 9780780390812
DOIs
Publication statusPublished - May 2005
Event2005 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, United States
Duration: 9 May 200511 May 2005
https://ieeexplore.ieee.org/xpl/conhome/10047/proceeding

Publication series

NameInternational Conference on Integrated Circuit Design and Technology, ICICDT
ISSN (Print)2381-3555

Conference

Conference2005 International Conference on Integrated Circuit Design and Technology, ICICDT
Country/TerritoryUnited States
CityAustin
Period9/05/0511/05/05
Internet address

Scopus Subject Areas

  • Engineering(all)

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