Abstract
Timing is a critical issue in electronic design automation (EDA). To reduce the delay of a net, an important strategy is to minimize the path lengths from the source to the sinks. However, minimizing the path lengths will inevitably sacrifice the total wirelength. To balance the two objectives, researchers use shallow-light tree (SLT) to model and optimize the problem. In this article, we introduce MALT, a novel approach that uses a neural network to guide the construction of Steiner shallow-light trees. The constructed trees are further refined by a dynamic programming-based branch merging algorithm, which improves the wirelength without sacrificing the path lengths of any sinks. Our experimental results demonstrate that the proposed framework achieves significant improvements over both state-of-the-art traditional SLT generation algorithms and existing machine learning enhanced methods.
| Original language | English |
|---|---|
| Article number | 79 |
| Pages (from-to) | 1-15 |
| Number of pages | 15 |
| Journal | ACM Transactions on Design Automation of Electronic Systems |
| Volume | 31 |
| Issue number | 4 |
| Early online date | 19 Mar 2026 |
| DOIs | |
| Publication status | Published - Jul 2026 |
UN SDGs
This output contributes to the following UN Sustainable Development Goals (SDGs)
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SDG 9 Industry, Innovation, and Infrastructure
User-Defined Keywords
- EDA
- machine learning
- shallow-light tree
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