Lithography-aware layout modification considering performance impact

As regular design rules become necessary in sub-45nm node circuit design, 1-D design has shown its advantages and has drawn intensive research interest. In 1-D design, line-end gaps are the main sources of printing difficulties. Recently, we [5] demonstrated that printability can be significantly improved by intelligent (litho-aware) rearrangement of the gap distribution with techniques such as line-end extension and dummy insertion. Note that poly/gate redistribution techniques require layout modification of the original layout and thus will impact circuit performance and power consumption. Such potentially undesirable impacts on performance and power were not considered in [5] and deserve a careful investigation, which is the subject of our study. In this paper, we present performance-driven gate redistribution algorithms which consider bounds on line-end extension. Experimental results demonstrate the feasibility of our algorithms, and lithography simulation and circuit analysis show the trend of the trade off between printability, delay, and power.