Late Breaking Results: Distributed Timing Analysis at Scale

Tsung-Wei Huang; Chun-Xun Lin; Martin D. F. Wong

doi:10.1145/3316781.3322470

Late Breaking Results: Distributed Timing Analysis at Scale

Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

Abstract

As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless integrable to existing EDA applications, (3) enables transparent resource management, (4) has robust fault-tolerant control. We evaluate the distributed timer using a set of large industry benchmarks on a cluster with 24 nodes. The results show that the proposed timer achieves full accuracy over all designs with high performance and good scalability.

Original language	English
Title of host publication	56th ACM/IEEE Design Automation Conference - Proceedings 2019
Publisher	Association for Computing Machinery (ACM)
Pages	1-2
Number of pages	2
ISBN (Electronic)	9781450367257
ISBN (Print)	9781728124261
DOIs	https://doi.org/10.1145/3316781.3322470
Publication status	Published - Jun 2019
Event	56th ACM/IEEE Design Automation Conference, DAC 2019 - Las Vegas, United States Duration: 2 Jun 2019 → 6 Jun 2019 https://ieeexplore.ieee.org/xpl/conhome/8791231/proceeding (Link to conference proceedings) https://dl.acm.org/doi/proceedings/10.1145/3316781 (Link to conference proceedings)

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Conference

Conference	56th ACM/IEEE Design Automation Conference, DAC 2019
Country/Territory	United States
City	Las Vegas
Period	2/06/19 → 6/06/19
Internet address	https://ieeexplore.ieee.org/xpl/conhome/8791231/proceeding (Link to conference proceedings) https://dl.acm.org/doi/proceedings/10.1145/3316781 (Link to conference proceedings)

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10.1145/3316781.3322470

Cite this

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title = "Late Breaking Results: Distributed Timing Analysis at Scale",

abstract = "As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless integrable to existing EDA applications, (3) enables transparent resource management, (4) has robust fault-tolerant control. We evaluate the distributed timer using a set of large industry benchmarks on a cluster with 24 nodes. The results show that the proposed timer achieves full accuracy over all designs with high performance and good scalability.",

author = "Tsung-Wei Huang and Chun-Xun Lin and Wong, {Martin D. F.}",

note = "Funding information: This work is supported by NSF Grant CCF-1718883 and DARPA Grant FA-650-18-2-7843.; 56th ACM/IEEE Design Automation Conference, DAC 2019 ; Conference date: 02-06-2019 Through 06-06-2019",

year = "2019",

month = jun,

doi = "10.1145/3316781.3322470",

language = "English",

isbn = "9781728124261",

series = "ACM/IEEE Design Automation Conference - Proceedings",

publisher = "Association for Computing Machinery (ACM)",

pages = "1--2",

booktitle = "56th ACM/IEEE Design Automation Conference - Proceedings 2019",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/8791231/proceeding, https://dl.acm.org/doi/proceedings/10.1145/3316781",

}

Huang, T-W, Lin, C-X & Wong, MDF 2019, Late Breaking Results: Distributed Timing Analysis at Scale. in 56th ACM/IEEE Design Automation Conference - Proceedings 2019., 229, ACM/IEEE Design Automation Conference - Proceedings, Association for Computing Machinery (ACM), pp. 1-2, 56th ACM/IEEE Design Automation Conference, DAC 2019, Las Vegas, Nevada, United States, 2/06/19. https://doi.org/10.1145/3316781.3322470

Late Breaking Results: Distributed Timing Analysis at Scale. / Huang, Tsung-Wei; Lin, Chun-Xun; Wong, Martin D. F.
56th ACM/IEEE Design Automation Conference - Proceedings 2019. Association for Computing Machinery (ACM), 2019. p. 1-2 229 (ACM/IEEE Design Automation Conference - Proceedings).

Research output: Chapter in book/report/conference proceeding › Chapter › peer-review

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AU - Huang, Tsung-Wei

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AU - Wong, Martin D. F.

N1 - Funding information: This work is supported by NSF Grant CCF-1718883 and DARPA Grant FA-650-18-2-7843.

PY - 2019/6

Y1 - 2019/6

N2 - As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless integrable to existing EDA applications, (3) enables transparent resource management, (4) has robust fault-tolerant control. We evaluate the distributed timer using a set of large industry benchmarks on a cluster with 24 nodes. The results show that the proposed timer achieves full accuracy over all designs with high performance and good scalability.

AB - As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless integrable to existing EDA applications, (3) enables transparent resource management, (4) has robust fault-tolerant control. We evaluate the distributed timer using a set of large industry benchmarks on a cluster with 24 nodes. The results show that the proposed timer achieves full accuracy over all designs with high performance and good scalability.

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UR - https://ieeexplore.ieee.org/document/8806927

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DO - 10.1145/3316781.3322470

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SN - 9781728124261

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BT - 56th ACM/IEEE Design Automation Conference - Proceedings 2019

PB - Association for Computing Machinery (ACM)

T2 - 56th ACM/IEEE Design Automation Conference, DAC 2019

Y2 - 2 June 2019 through 6 June 2019

ER -

Late Breaking Results: Distributed Timing Analysis at Scale

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