Late Breaking Results: Distributed Timing Analysis at Scale

Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong

Research output: Chapter in book/report/conference proceedingChapterpeer-review


As the design complexities continue to grow, the need to efficiently analyze circuit timing with billions of transistors is quickly becoming the major bottleneck to the overall chip design flow. In this work we introduce a distributed timer that (1) has scalable performance, (2) can be seamless integrable to existing EDA applications, (3) enables transparent resource management, (4) has robust fault-tolerant control. We evaluate the distributed timer using a set of large industry benchmarks on a cluster with 24 nodes. The results show that the proposed timer achieves full accuracy over all designs with high performance and good scalability.
Original languageEnglish
Title of host publication56th ACM/IEEE Design Automation Conference - Proceedings 2019
PublisherAssociation for Computing Machinery (ACM)
Number of pages2
ISBN (Electronic)9781450367257
ISBN (Print)9781728124261
Publication statusPublished - Jun 2019
Event56th ACM/IEEE Design Automation Conference, DAC 2019 - Las Vegas, United States
Duration: 2 Jun 20196 Jun 2019 (Link to conference proceedings) (Link to conference proceedings)

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X


Conference56th ACM/IEEE Design Automation Conference, DAC 2019
Country/TerritoryUnited States
CityLas Vegas
Internet address


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