I/O clustering in design cost and performance optimization for flip-chip design

Hung Ming Chen; I Min Liu; Martin D. F. Wong; Muzhou Shao; Li Da Huang

doi:10.1109/ICCD.2004.1347978

I/O clustering in design cost and performance optimization for flip-chip design

Hung Ming Chen, I Min Liu, Martin D. F. Wong, Muzhou Shao, Li Da Huang

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

9 Citations (Scopus)

Abstract

I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the chip. However, because of I/O placement constraints in design cost and performance, I/O buffer planning becomes a pressing problem. During the early stages of circuits and packaging co-design, I/O layout should be evaluated to optimize design cost and to avoid product failures. In this paper, our objective is to better an existing/initial standard cell placement by I/O clustering, considering design cost reduction and signal integrity preservation. We formulate it as a minimum cost flow problem minimizing αW + βD, where W is the I/O wirelength of the placement and D is the total voltage drop in the power network. The experimental results on some MCNC benchmarks show that our method achieves better timing performance and averagely over 30% design cost reduction when compared with the conventional design rule of thumb popularly used by circuit designers.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Computer Design
Subtitle of host publication	VLSI in Computers and Processors, ICCD 2004
Place of Publication	United States
Publisher	IEEE
Pages	562-567
Number of pages	6
ISBN (Print)	0769522319
DOIs	https://doi.org/10.1109/ICCD.2004.1347978
Publication status	Published - 13 Oct 2004
Event	22nd IEEE International Conference on Computer Design, ICCD 2004 - San Jose, United States Duration: 11 Oct 2004 → 13 Oct 2004 http://iccd.et.tudelft.nl/2004/ICCD2004MainPage.htm (Conference website) https://ieeexplore.ieee.org/xpl/conhome/9333/proceeding (Conference proceedings)

Publication series

Name	Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD
Publisher	IEEE
ISSN (Print)	1063-6404

Conference

Conference	22nd IEEE International Conference on Computer Design, ICCD 2004
Country/Territory	United States
City	San Jose
Period	11/10/04 → 13/10/04
Internet address	http://iccd.et.tudelft.nl/2004/ICCD2004MainPage.htm (Conference website) https://ieeexplore.ieee.org/xpl/conhome/9333/proceeding (Conference proceedings)

Scopus Subject Areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2004.1347978

Cite this

Chen, H. M., Liu, I. M., Wong, M. D. F., Shao, M., & Huang, L. D. (2004). I/O clustering in design cost and performance optimization for flip-chip design. In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004 (pp. 562-567). (Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD). IEEE. https://doi.org/10.1109/ICCD.2004.1347978

Chen, Hung Ming ; Liu, I Min ; Wong, Martin D. F. et al. / I/O clustering in design cost and performance optimization for flip-chip design. Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. United States : IEEE, 2004. pp. 562-567 (Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD).

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title = "I/O clustering in design cost and performance optimization for flip-chip design",

abstract = "I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the chip. However, because of I/O placement constraints in design cost and performance, I/O buffer planning becomes a pressing problem. During the early stages of circuits and packaging co-design, I/O layout should be evaluated to optimize design cost and to avoid product failures. In this paper, our objective is to better an existing/initial standard cell placement by I/O clustering, considering design cost reduction and signal integrity preservation. We formulate it as a minimum cost flow problem minimizing αW + βD, where W is the I/O wirelength of the placement and D is the total voltage drop in the power network. The experimental results on some MCNC benchmarks show that our method achieves better timing performance and averagely over 30% design cost reduction when compared with the conventional design rule of thumb popularly used by circuit designers.",

author = "Chen, {Hung Ming} and Liu, {I Min} and Wong, {Martin D. F.} and Muzhou Shao and Huang, {Li Da}",

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doi = "10.1109/ICCD.2004.1347978",

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booktitle = "Proceedings of the IEEE International Conference on Computer Design",

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Chen, HM, Liu, IM, Wong, MDF, Shao, M & Huang, LD 2004, I/O clustering in design cost and performance optimization for flip-chip design. in Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD, IEEE, United States, pp. 562-567, 22nd IEEE International Conference on Computer Design, ICCD 2004, San Jose, California, United States, 11/10/04. https://doi.org/10.1109/ICCD.2004.1347978

I/O clustering in design cost and performance optimization for flip-chip design. / Chen, Hung Ming; Liu, I Min; Wong, Martin D. F. et al.
Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. United States: IEEE, 2004. p. 562-567 (Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Huang, Li Da

PY - 2004/10/13

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AB - I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the chip. However, because of I/O placement constraints in design cost and performance, I/O buffer planning becomes a pressing problem. During the early stages of circuits and packaging co-design, I/O layout should be evaluated to optimize design cost and to avoid product failures. In this paper, our objective is to better an existing/initial standard cell placement by I/O clustering, considering design cost reduction and signal integrity preservation. We formulate it as a minimum cost flow problem minimizing αW + βD, where W is the I/O wirelength of the placement and D is the total voltage drop in the power network. The experimental results on some MCNC benchmarks show that our method achieves better timing performance and averagely over 30% design cost reduction when compared with the conventional design rule of thumb popularly used by circuit designers.

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Chen HM, Liu IM, Wong MDF, Shao M, Huang LD. I/O clustering in design cost and performance optimization for flip-chip design. In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2004. United States: IEEE. 2004. p. 562-567. (Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD). doi: 10.1109/ICCD.2004.1347978

I/O clustering in design cost and performance optimization for flip-chip design

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