I/O clustering in design cost and performance optimization for flip-chip design

H. M. Chen, I Min Liu, Martin D. F. Wong

Research output: Contribution to journalJournal articlepeer-review

3 Citations (Scopus)


Input-output (I/O) placement has always been a concern in modern integrated circuit design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the chip. However, because of I/O placement constraints in design cost (DC) and performance, I/O buffer planning becomes a pressing problem. During the early stages of circuits and package co-design, I/O layout should be evaluated to optimize DC and to avoid product failures. The objective of this brief is to improve the existing/initial standard cell placement by I/O clustering, considering DC reduction and signal integrity preservation. The authors formulate it as a minimum cost flow problem that minimizes α.W + βD, where W is the I/O wirelength of the placement and D is the total voltage drop in the power network and, at the same time, reduces the number of I/O buffer blocks. The experimental results on some Microelectronics Center of North Carolina benchmarks show that the author's method averagely achieves better timing performance and over 32% DC reduction when compared with a conventional rule-ofthumb design that is popularly used by circuit designers.

Original languageEnglish
Pages (from-to)2552-2556
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number11
Early online date23 Oct 2006
Publication statusPublished - Nov 2006

Scopus Subject Areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

User-Defined Keywords

  • Chip-package co-design
  • Flip-chip design
  • Input-output (I/O) planning
  • Signal integrity


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