Integrated partitioning and scheduling for hardware/software co-design

Huiqun Liu; D. F. Wong

doi:10.1109/ICCD.1998.727125

Integrated partitioning and scheduling for hardware/software co-design

Huiqun Liu, D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

13 Citations (Scopus)

Abstract

Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

Original language	English
Title of host publication	Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998
Publisher	IEEE
Pages	609-614
Number of pages	6
ISBN (Print)	0818690992
DOIs	https://doi.org/10.1109/ICCD.1998.727125
Publication status	Published - 5 Oct 1998
Event	16th IEEE International Conference on Computer Design, ICCD 1998 - Austin, United States Duration: 5 Oct 1998 → 7 Oct 1998 https://ieeexplore.ieee.org/xpl/conhome/5873/proceeding (Conference proceedings)

Publication series

Name	Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors
ISSN (Print)	1063-6404
ISSN (Electronic)	2576-6996

Conference

Conference	16th IEEE International Conference on Computer Design, ICCD 1998
Country/Territory	United States
City	Austin
Period	5/10/98 → 7/10/98
Internet address	https://ieeexplore.ieee.org/xpl/conhome/5873/proceeding (Conference proceedings)

Access to Document

10.1109/ICCD.1998.727125

Cite this

@inproceedings{3dbab18c7b7943298c35baecec35115f,

title = "Integrated partitioning and scheduling for hardware/software co-design",

abstract = "Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.",

author = "Huiqun Liu and Wong, {D. F.}",

note = "This work was partially supported by the Texas Advanced Research Program under Grant No. 003658288 and by a grant from the Intel Corporation.; 16th IEEE International Conference on Computer Design, ICCD 1998 ; Conference date: 05-10-1998 Through 07-10-1998",

year = "1998",

month = oct,

day = "5",

doi = "10.1109/ICCD.1998.727125",

language = "English",

isbn = "0818690992",

series = "Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors",

publisher = "IEEE",

pages = "609--614",

booktitle = "Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/5873/proceeding",

}

Liu, H & Wong, DF 1998, Integrated partitioning and scheduling for hardware/software co-design. in Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998. Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors, IEEE, pp. 609-614, 16th IEEE International Conference on Computer Design, ICCD 1998, Austin, Texas, United States, 5/10/98. https://doi.org/10.1109/ICCD.1998.727125

Integrated partitioning and scheduling for hardware/software co-design. / Liu, Huiqun; Wong, D. F.
Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998. IEEE, 1998. p. 609-614 (Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - Integrated partitioning and scheduling for hardware/software co-design

AU - Liu, Huiqun

AU - Wong, D. F.

N1 - This work was partially supported by the Texas Advanced Research Program under Grant No. 003658288 and by a grant from the Intel Corporation.

PY - 1998/10/5

Y1 - 1998/10/5

N2 - Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

AB - Existing approaches to hardware/software co-design separate partitioning and scheduling as two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approach leads to sub-optimal results. In this paper, we explore an integrated hardware/software partitioning and scheduling strategy, where the partitioning process uses the information provided by the scheduling solution as a guide. We present an efficient algorithm for partitioning and scheduling the tasks for execution on the given software (2 CPUs) and hardware (k ASICs or FPGAs) resources with the objective of minimizing the total execution time and the hardware cost. Our algorithm has produced good results for all the task graphs in our experiments.

UR - https://www.scopus.com/record/display.uri?eid=2-s2.0-0032303533&origin=resultslist&sort=plf-f&src=s&sid=6b7d04ef7e4b9a9aa522d79c3a609fef&sot=b&sdt=b&s=TITLE-ABS-KEY%28%22Integrated+partitioning+and+scheduling+for+hardware%2Fsoftware+co-design%22%29&sl=26&sessionSearchId=6b7d04ef7e4b9a9aa522d79c3a609fef

U2 - 10.1109/ICCD.1998.727125

DO - 10.1109/ICCD.1998.727125

M3 - Conference proceeding

SN - 0818690992

T3 - Proceedings - IEEE International Conference on Computer Design (ICCD): VLSI in Computers and Processors

SP - 609

EP - 614

BT - Proceedings of The 16th IEEE International Conference on Computer Design, ICCD 1998

PB - IEEE

T2 - 16th IEEE International Conference on Computer Design, ICCD 1998

Y2 - 5 October 1998 through 7 October 1998

ER -

Integrated partitioning and scheduling for hardware/software co-design

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this