Integrated floorplanning and interconnect planning

Hung-Ming Chen, Hai Zhou, Evangeline F.Y. Young, D. F. Wong, H. H. Yang, N. Sherwani

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

57 Citations (Scopus)


VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early as possible. We propose a method to combine interconnect planning with floorplanning. Our approach is based on the Wong-Liu (1986) floorplaning algorithm. When the positions, orientations, and shapes of the cells are decided, the pin positions and routing of the interconnects are decided as well. We use a multi-stage simulated annealing approach in which different interconnect planning methods are used in different ranges of temperature to reduce running time. A temperature adjustment scheme is designed to give smooth transitions between different stages of simulated annealing. Experimental results show that our approach performs well.
Original languageEnglish
Title of host publication1999 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
Number of pages4
ISBN (Print)0780358325
Publication statusPublished - 7 Nov 1999
Event1999 IEEE International Conference on Computer-Aided Design, ICCAD 1999 - San Jose, United States
Duration: 7 Nov 199911 Nov 1999 (Conference proceedings)

Publication series

NameIEEE International Conference on Computer-Aided Design


Conference1999 IEEE International Conference on Computer-Aided Design, ICCAD 1999
Country/TerritoryUnited States
CitySan Jose
Internet address


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