Integrated delay analysis of regulated ATM switch

Joseph K Y Ng*, S. Song, W. Zhao

*Corresponding author for this work

Research output: Contribution to conferenceConference paperpeer-review

8 Citations (Scopus)


In this paper, we present an efficient and effective method to derive the worst case delay in an ATM switch. In an ATM switch, admitting a hard real-time connection requires the delays of cells belonging to the connection meeting their deadline without violating the guarantees already provided to connections that are currently active. Previous studies have shown that the real-time connection traffic and the available service can both be described by piece-wise linear functions in terms of time. By utilizing the inverse of the arrival and service functions, we obtain an efficient and effective method to compute the worst case delay of a connection to an ATM switch. We analyze and compare the performance of an ATM switch with priority driven and FIFO scheduling policies under different utilization. We also compare the performance using our proposed 'integrated' method with the traditional 'independent' method. From simulation experiments, we found out that our method always obtain a higher admission probability and a better estimation of cell delay within an ATM switch.

Original languageEnglish
Number of pages12
Publication statusPublished - 1997
EventProceedings of the 1997 18th IEEE Real-Time Systems Symposium - San Francisco, CA, USA
Duration: 2 Dec 19975 Dec 1997


ConferenceProceedings of the 1997 18th IEEE Real-Time Systems Symposium
CitySan Francisco, CA, USA

Scopus Subject Areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications


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