Improving voltage assignment by outlier detection and incremental placement

Design for low power has become a key requirement in today's SoC design, especially for mobile applications. Multi-Vdd is an effective method to reduce both leakage and dynamic power. In a multi-Vdd design, cells of different supply voltages are often grouped into a small number of voltage islands, in order to avoid complex power supply system and excessive amount of level shifters. Recently, [9] proposed an elegant algorithm for voltage island grouping based on the physical proximity of the critical cells in a post-placement voltage assignment, and [10] proposed an efficient algorithm for voltage assignment which not only meets timing but also forms good proximity of the critical cells. However, due to insufficient slack, a few isolated critical cells (called outliers) may still exist in the resulting voltage assignment, causing disproportionately expensive penalty to the final voltage island grouping. In this paper, we propose a novel approach to improve the voltage assignment by automatic outlier detection followed by incremental placement. The outlier detection is based on a modified algorithm for the facility location problem. The incremental placement is guided by setting proper constraints on the paths containing the detected outliers, such that the outliers can be eliminated later. Our experiments on industry designs show that our algorithm leads to 12% - 54% improvement in the final voltage island grouping, with quick turn around time.