Implementation and analysis of AES encryption on GPU

Qinjian Li; Chengwen Zhong; Kaiyong Zhao; Xinxin Mei; Xiaowen CHU

doi:10.1109/HPCC.2012.119

Implementation and analysis of AES encryption on GPU

Qinjian Li^*, Chengwen Zhong, Kaiyong Zhao, Xinxin Mei, Xiaowen CHU

^*Corresponding author for this work

Department of Computer Science

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

89 Citations (Scopus)

Abstract

GPU is continuing its trend of vastly outperforming CPU while becoming more general purpose. In order to improve the efficiency of AES algorithm, this paper proposed a CUDA implementation of Electronic Codebook (ECB) mode encoding process and Cipher Feedback (CBC) mode decoding process on GPU. In our implementation, the frequently accessed T-boxes were allocated on on-chip shared memory and the granularity that one thread handles a 16 Bytes AES block was adopted. Finally, we achieved the highest performance of around 60 Gbps throughput on NVIDIA Tesla C2050 GPU, which runs up to 50 times faster than a sequential implementation based on Intel Core i7-920 2.66GHz CPU. In addition, we discussed the optimization under some practical application scenarios such as overlapping GPU processing and data transfer.

Original language	English
Title of host publication	Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012
Pages	843-848
Number of pages	6
DOIs	https://doi.org/10.1109/HPCC.2012.119
Publication status	Published - 2012
Event	14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012 - Liverpool, United Kingdom Duration: 25 Jun 2012 → 27 Jun 2012 https://ieeexplore.ieee.org/xpl/conhome/6331801/proceeding

Publication series

Name	Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012

Conference

Conference	14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012
Country/Territory	United Kingdom
City	Liverpool
Period	25/06/12 → 27/06/12
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6331801/proceeding

Scopus Subject Areas

Software

User-Defined Keywords

AES
Cipher Feedback
CUDA
Electronic Codebook
GPU
Parellel computing

Access to Document

10.1109/HPCC.2012.119

Cite this

Li, Q., Zhong, C., Zhao, K., Mei, X., & CHU, X. (2012). Implementation and analysis of AES encryption on GPU. In Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012 (pp. 843-848). Article 6332257 (Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012). https://doi.org/10.1109/HPCC.2012.119

Li, Qinjian ; Zhong, Chengwen ; Zhao, Kaiyong et al. / Implementation and analysis of AES encryption on GPU. Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012. 2012. pp. 843-848 (Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012).

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abstract = "GPU is continuing its trend of vastly outperforming CPU while becoming more general purpose. In order to improve the efficiency of AES algorithm, this paper proposed a CUDA implementation of Electronic Codebook (ECB) mode encoding process and Cipher Feedback (CBC) mode decoding process on GPU. In our implementation, the frequently accessed T-boxes were allocated on on-chip shared memory and the granularity that one thread handles a 16 Bytes AES block was adopted. Finally, we achieved the highest performance of around 60 Gbps throughput on NVIDIA Tesla C2050 GPU, which runs up to 50 times faster than a sequential implementation based on Intel Core i7-920 2.66GHz CPU. In addition, we discussed the optimization under some practical application scenarios such as overlapping GPU processing and data transfer.",

keywords = "AES, Cipher Feedback, CUDA, Electronic Codebook, GPU, Parellel computing",

author = "Qinjian Li and Chengwen Zhong and Kaiyong Zhao and Xinxin Mei and Xiaowen CHU",

note = "Copyright: Copyright 2012 Elsevier B.V., All rights reserved.; 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012 ; Conference date: 25-06-2012 Through 27-06-2012",

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doi = "10.1109/HPCC.2012.119",

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series = "Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012",

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Li, Q, Zhong, C, Zhao, K, Mei, X & CHU, X 2012, Implementation and analysis of AES encryption on GPU. in Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012., 6332257, Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012, pp. 843-848, 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012, Liverpool, United Kingdom, 25/06/12. https://doi.org/10.1109/HPCC.2012.119

Implementation and analysis of AES encryption on GPU. / Li, Qinjian; Zhong, Chengwen; Zhao, Kaiyong et al.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012. 2012. p. 843-848 6332257 (Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AB - GPU is continuing its trend of vastly outperforming CPU while becoming more general purpose. In order to improve the efficiency of AES algorithm, this paper proposed a CUDA implementation of Electronic Codebook (ECB) mode encoding process and Cipher Feedback (CBC) mode decoding process on GPU. In our implementation, the frequently accessed T-boxes were allocated on on-chip shared memory and the granularity that one thread handles a 16 Bytes AES block was adopted. Finally, we achieved the highest performance of around 60 Gbps throughput on NVIDIA Tesla C2050 GPU, which runs up to 50 times faster than a sequential implementation based on Intel Core i7-920 2.66GHz CPU. In addition, we discussed the optimization under some practical application scenarios such as overlapping GPU processing and data transfer.

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Li Q, Zhong C, Zhao K, Mei X, CHU X. Implementation and analysis of AES encryption on GPU. In Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012. 2012. p. 843-848. 6332257. (Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012). doi: 10.1109/HPCC.2012.119

Implementation and analysis of AES encryption on GPU

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