TY - JOUR
T1 - High performance hardware architecture for singular spectrum analysis of Hankel tensors
AU - Huang, Wei pei
AU - Kwan, Bowen P.Y.
AU - DING, Weiyang
AU - Min, Biao
AU - Cheung, Ray C.C.
AU - Qi, Liqun
AU - Yan, Hong
N1 - Funding Information:
This work is supported by the Hong Kong Research Grants Council (Project C1007-15G).
PY - 2019/2
Y1 - 2019/2
N2 - This paper presents a hardware architecture for singular spectrum analysis of Hankel tensors, including computation of tucker decomposition, tensor reconstruction and final Hankelization. In the proposed design, we explore two level of optimization. First, in algorithm level, we optimize the calculation process by exploiting the Hankel property to reduce the computation complexity and on-chip BRAM resource usage. Secondly, in hardware level, parallelism is explored for acceleration. Resource sharing is applied to reduce look-up tables (LUTs) usage. To enable flexibility, the number of processing elements (PEs) can be changed through parameter setting. Our proposed design is implemented on Field-Programmable Gate Arrays (FPGAs) to process third order tensors. Experiment results show that our design achieve a speed-up from 172 to 1004 compared with CPU implementation via Intel MKL and 5 to 40 compared with GPU implementation.
AB - This paper presents a hardware architecture for singular spectrum analysis of Hankel tensors, including computation of tucker decomposition, tensor reconstruction and final Hankelization. In the proposed design, we explore two level of optimization. First, in algorithm level, we optimize the calculation process by exploiting the Hankel property to reduce the computation complexity and on-chip BRAM resource usage. Secondly, in hardware level, parallelism is explored for acceleration. Resource sharing is applied to reduce look-up tables (LUTs) usage. To enable flexibility, the number of processing elements (PEs) can be changed through parameter setting. Our proposed design is implemented on Field-Programmable Gate Arrays (FPGAs) to process third order tensors. Experiment results show that our design achieve a speed-up from 172 to 1004 compared with CPU implementation via Intel MKL and 5 to 40 compared with GPU implementation.
KW - Hankel tensor
KW - Hardware architecture
KW - Higher-order singular value decomposition (HOSVD)
KW - Tucker decomposition(TKD)
UR - http://www.scopus.com/inward/record.url?scp=85056608735&partnerID=8YFLogxK
U2 - 10.1016/j.micpro.2018.10.004
DO - 10.1016/j.micpro.2018.10.004
M3 - Journal article
AN - SCOPUS:85056608735
SN - 0141-9331
VL - 64
SP - 120
EP - 127
JO - Microprocessors and Microsystems
JF - Microprocessors and Microsystems
ER -