High performance hardware architecture for singular spectrum analysis of Hankel tensors

Wei pei Huang, Bowen P.Y. Kwan, Weiyang DING, Biao Min, Ray C.C. Cheung*, Liqun Qi, Hong Yan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

This paper presents a hardware architecture for singular spectrum analysis of Hankel tensors, including computation of tucker decomposition, tensor reconstruction and final Hankelization. In the proposed design, we explore two level of optimization. First, in algorithm level, we optimize the calculation process by exploiting the Hankel property to reduce the computation complexity and on-chip BRAM resource usage. Secondly, in hardware level, parallelism is explored for acceleration. Resource sharing is applied to reduce look-up tables (LUTs) usage. To enable flexibility, the number of processing elements (PEs) can be changed through parameter setting. Our proposed design is implemented on Field-Programmable Gate Arrays (FPGAs) to process third order tensors. Experiment results show that our design achieve a speed-up from 172 to 1004 compared with CPU implementation via Intel MKL and 5 to 40 compared with GPU implementation.

Original languageEnglish
Pages (from-to)120-127
Number of pages8
JournalMicroprocessors and Microsystems
Volume64
DOIs
Publication statusPublished - Feb 2019

Scopus Subject Areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

User-Defined Keywords

  • Hankel tensor
  • Hardware architecture
  • Higher-order singular value decomposition (HOSVD)
  • Tucker decomposition(TKD)

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