High-Level Synthesis for Minimizing Power Side-Channel Information Leakage

S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen*

*Corresponding author for this work

Research output: Chapter in book/report/conference proceedingChapterpeer-review


The Internet of Things (IoT) and cloud computing rely on strong confidence in security of data privacy and confidentiality. Power side-channel information leakage remains an ongoing threat in untrusted environment, but its countermeasures require expert-level security knowledge for efficient implementation, limiting adoption. This work addresses this need by presenting the first high-level synthesis (HLS) flow with primary focus on side-channel leakage reduction. Minimal security annotation to the high-level C-code is sufficient to perform automatic analysis of security critical operations with corresponding insertion of countermeasures. Additionally, imbalanced branches are identified and balanced to shrink the possible attack surface. For practicality, the flow can meet both resource and information leakage constraints. The presented flow is extensively evaluated on established HLS benchmarks and a general IoT benchmark. Under identical resource constraints, leakage is reduced between 32 and 72% compared to the reference. Under leakage target, the constraints are achieved with 31-81% less resource overhead.

Original languageEnglish
Title of host publicationBehavioral Synthesis for Hardware Security
EditorsSrinivas Katkoori, Sheikh Ariful Islam
Place of PublicationCham
PublisherSpringer International Publishing
Number of pages27
ISBN (Electronic)9783030788414
ISBN (Print)9783030788407, 9783030788438
Publication statusPublished - 8 Feb 2022

Scopus Subject Areas

  • Engineering(all)
  • Computer Science(all)

User-Defined Keywords

  • Security
  • Field programmable gate array
  • Side-channel attacks
  • Side-channel leakage defenses
  • Differential power analysis
  • High-level synthesis


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